Open-source alternatives to Chisel

picorv32 is a size-optimized RISC-V CPU core and synthesizable processor IP designed for integration into FPGA and ASIC hardware designs. It serves as an open-source CPU architecture and embedded system-on-chip component that implements a standard RISC-V instruction set. The design features a modular architecture that allows for the integration of external coprocessors to implement custom non-branching instructions. It includes a parameterized integer unit with configurable multiplication and division cores to balance performance against total logic gate count. The project covers a broad ran

Clash is a functional hardware compiler and hardware description language compiler that translates strongly typed functional programs written in Haskell into synthesizable VHDL, Verilog, and SystemVerilog code. It serves as a development tool allowing digital designers to write hardware descriptions in functional languages and compile them directly to FPGA targets and physical netlists. The compilation infrastructure covers structural hardware compilation, including graph-based code normalization, functional language translation, and netlist generation. It features type-level clock domain saf

This project consists of technical instructional guides and a structured computer science curriculum designed to teach the construction of a full computing stack from transistors up to a web browser. It provides a 12-week educational course that covers the fundamental domains of computer architecture and digital logic design. The curriculum is distinguished by its first-principles approach, guiding the learner through the engineering of CPUs, FPGAs, and PCBs using digital logic and hardware description languages. It includes specific syllabi for building a hardware design, a TCP/IP network st

Rocket-chip is a framework for the parametric design, synthesis, and verification of RISC-V based processors and system-on-chip hardware. It functions as a generator that converts high-level specifications into synthesizable Verilog files for FPGA or ASIC implementation. The project utilizes a Scala-based hardware description framework to produce customizable pipelined processor cores, memory hierarchies, and peripheral devices. It employs a parameter-driven model and a two-phase negotiation process to resolve hardware interface specifications between modules during the elaboration phase. Th

Yosys is a digital logic synthesizer and RTL synthesis tool that transforms hardware description language code into optimized gate-level representations. It functions as a hardware logic optimizer and formal verification tool, providing a framework to convert generic circuit representations into specific technology library cells for targeted hardware platforms. The project serves as a hardware design automator through a scriptable environment used to execute sequences of synthesis commands. This automation allows for the management of complex digital hardware workflows, integrating RTL design

LiteX is an FPGA SoC development suite and SoC builder framework used to programmatically design system-on-chips. It provides a hardware description toolchain that uses a scriptable framework to define hardware layouts and automate the generation of hardware description language code. The project distinguishes itself by orchestrating multiple vendor and open-source toolchains to synthesize digital logic and generate deployable bitstreams. It supports multi-language logic integration, allowing disparate hardware description languages to be combined into a single project. The framework covers

This project is an open-source computer-aided design toolchain designed for the synthesis, placement, and routing of hardware designs onto programmable logic architectures. It serves as a comprehensive framework for research and development, enabling the transformation of hardware description language designs into optimized netlists and physical implementation files. By providing a modular pipeline, the system facilitates the entire flow from initial logic synthesis to the generation of configuration data for programmable hardware devices. The toolchain distinguishes itself through its focus

Cirq is a Python quantum computing framework used for designing, simulating, and executing quantum circuits on Noisy Intermediate-Scale Quantum (NISQ) hardware. It serves as a quantum circuit simulator and noise modeler, as well as a tool for the implementation of quantum algorithms. The framework provides a specialized interface for NISQ hardware, allowing users to map logical quantum circuits to physical device topologies while validating hardware connectivity and gate constraints. It distinguishes itself through integrated noise modeling, applying depolarizing and damping channels to mimic

Qiskit is a quantum computing software development kit used for designing, simulating, and executing quantum circuits on physical hardware and simulators. It functions as a quantum algorithm framework, a circuit simulator, and a vendor-agnostic hardware interface for dispatching workloads across diverse providers. The project features a quantum circuit transpiler that optimizes abstract designs to match the specific basis gates and qubit connectivity of target hardware. It employs a pass-based transpilation pipeline and symbolic instruction translation to convert high-level circuits into hard

darkriscv is a collection of tools and projects for RISC-V processor implementation, hardware debugging, and automated FPGA synthesis. It provides a hardware design that implements a RISC-V processor core and system components for deployment on programmable logic. The project includes a hardware debugger with a command-line interface for verifying processor state by manipulating registers and dumping memory on a hardware target. It also features a set of scripts and project files to automate the synthesis and programming of hardware designs within a Linux environment. The codebase covers har

Digital-Logic-Sim is a digital logic simulator and interactive circuit designer used for building and simulating digital hardware circuits. It functions as a visual editor and logic state visualizer that allows for the creation of complex digital logic models using logic gates, wires, and custom chips. The system includes a custom logic chip builder, enabling the grouping of basic logic gates into reusable components to create layered hardware architectures. Users can monitor these designs through a logic state visualizer that displays signal states and memory values using light indicators an

GHDL is a compiler and simulator for VHDL hardware descriptions. It functions as a multi-pass analysis elaborator that resolves design hierarchies and dependencies to prepare hardware descriptions for simulation or synthesis. The project transforms VHDL source code into executable binaries for high-speed digital design verification and serves as a synthesis tool that converts descriptions into structural netlists compatible with vendor or open-source flows. It also implements the Language Server Protocol to provide static analysis, autocomplete, and code navigation for VHDL files. The toolse

xq-py is a numerical quantum computing library and software emulator used to execute quantum algorithms. It functions as a quantum virtual machine that simulates quantum circuits and state vectors through the use of linear algebra and complex number arrays. The project provides a virtual environment for developing and verifying quantum logic. It models multi-qubit systems by utilizing tensor-product expansion and unitary gate applications to simulate quantum state vectors and calculate probabilistic state collapse. The simulation is supported by a numerical backend that handles the matrix-ba

This project is a quantum computing educational resource and implementation library. It provides a collection of interactive notebooks and guides designed for learning quantum programming, developing algorithms, and simulating quantum circuits. The resource includes tutorials for implementing standard quantum algorithms and creating custom circuit passes. It specifically covers quantum hardware control, providing instructions on scheduling raw microwave or laser pulses to implement precise gates at the physical layer. The materials cover the broader surface of quantum circuit design, includi

Bitwise is a computer architecture education kit and a comprehensive set of guides for building a custom CPU, operating system, and compiler from scratch. It serves as a CPU design tutorial and a practical framework for implementing a unique instruction set architecture. The project provides a custom instruction set architecture toolchain, including resources for creating a matching assembler and compiler. It further includes a hardware development guide for synthesizing computer components and peripheral controllers for deployment on programmable logic devices and FPGAs. The kit covers full

Bit is a component-based development platform and monorepo orchestrator used to build, manage, and share reusable software components across projects. It functions as a system for modular software architecture, providing a component registry for publishing and distributing independent software modules via remote scopes. The platform distinguishes itself through lane-based versioning, which isolates feature development into parallel tracks for comparison and merging. It utilizes a scope-based namespace registry to organize components into hierarchical groups and employs environment-driven comp

iView WeApp is a UI component library designed specifically for building WeChat mini-program interfaces. It provides a set of reusable, pre-styled components that developers can compose into mobile pages and layouts, following the native WeChat component model where each component has its own template, style, script, and configuration files. The library organizes the user interface as a tree of self-contained components that manage their own view and logic, with a clear separation between behavior in JavaScript files and visual structure in WXML templates. Components are packaged as independe

Digital is a digital logic circuit simulator and hardware design verification tool. It provides a visual environment for designing, testing, and verifying electronic circuits using event-based simulation and automated logic synthesis. The platform functions as a logic synthesis tool that applies boolean algebra to minimize gate configurations and convert truth tables into efficient hardware. It also serves as an HDL export tool, translating visual circuit graphs into VHDL or Verilog code, and as a CPLD deployment tool that generates JEDEC files for flashing programmable logic chips. The soft

CodeIgniter is a PHP web framework built on the Model-View-Controller pattern, designed for building full-stack web applications. It provides a lightweight toolkit with minimal configuration, organizing application logic into controllers, models, and views for clean separation of concerns. The framework includes a fluent query builder for constructing SQL statements programmatically, PSR-4 autoloading with namespace mapping, and a service-based dependency injection container for managing shared class instances. The framework distinguishes itself through its comprehensive set of built-in tools

Ractive is an open-source JavaScript framework for building reactive user interfaces where the DOM automatically updates when underlying data changes. It is fundamentally a declarative data binding library that synchronizes data between the model and the view, enabling two-way binding without manual DOM manipulation, and operates as a template-based component system for composing markup, styles, and logic into reusable UI components. The framework distinguishes itself through a plugin-extensible architecture that allows custom components, adaptors, and extensions to be registered without modi

This project is a React UI component library and design system framework. It provides a collection of reusable interface elements and an accessible component toolkit designed to meet web accessibility standards and responsive design requirements. The framework enforces visual uniformity through a design system that uses centralized design tokens for colors, spacing, and typography. It includes a standardized SVG icon set to provide consistent visual cues and markers across user interfaces. The library covers the implementation of design systems through token-based styling and the development

Yii is a full-stack PHP web framework and component-based system designed for building dynamic websites and RESTful services. It operates as an MVC application framework that separates business logic from the user interface and includes a built-in object-relational mapper for interacting with databases. The project provides a comprehensive command line toolset for project bootstrapping, automated code generation, and the execution of background tasks. It utilizes a component-based architecture and a service locator to manage dependency injection and object lifecycles. The framework covers a

Z3 is an automated theorem prover and satisfiability modulo theories solver designed to determine the validity of complex logical formulas. It functions as a formal verification framework, enabling the systematic checking of hardware and software system specifications against defined logical constraints to identify inconsistencies or design flaws. The engine distinguishes itself through a combination of theory-specific decision procedures and symbolic execution capabilities. It employs conflict-driven clause learning and backtracking search algorithms to prune search spaces, while maintaining

LoopBack Next is a Node.js API framework used for building REST and multi-protocol APIs. It functions as an OpenAPI server implementation that can either generate machine-readable specifications from code or produce implementation controllers and models from existing specifications. The framework distinguishes itself through a central dependency injection container and a repository-pattern data access layer. This architecture decouples application logic from component construction and persistent storage, allowing for a pluggable system where data sources and business logic are isolated throug

This is a style guide for structuring AngularJS applications using a component-based architecture. It provides a set of conventions for organizing code into self-contained modules, each encapsulating its own logic, templates, and routing. The guide promotes a modular application structure built from root, component, common, and feature modules to improve maintainability and reusability. The guide establishes a one-way data flow pattern where parent components pass data to children through bindings, and children communicate changes back up through events. It distinguishes between stateful comp

This project is an expressive text-to-speech foundation model and voice cloning system designed to synthesize human-like speech with emotional nuance and high fidelity. It functions as a finetunable speech model that can generate audio mimicking a specific person using a reference voice sample. The system distinguishes itself through a high-performance inference engine that utilizes memory caching and hardware compilation to reduce latency during the audio generation process. It further allows for synthesis quality improvements by training the language model on custom datasets consisting of a

Arco Design is a React UI component library and design system framework used to build professional web interfaces. It provides a collection of pre-built visual elements and layouts designed to maintain a consistent design language across applications. The system features a token-based theming engine that utilizes hierarchical design variables and CSS variables to enable granular visual customization. This allows for the modification of global and component-level styles through a dedicated theme editor or loader to align the interface with specific brand identities. The framework supports ent