OpenXiangShan/XiangShan

Features

• RISC-V Processor Cores - Provides a high-performance synthesizable implementation of the RISC-V processor core.
• Superscalar Out-of-Order Execution - Implements a high-performance superscalar out-of-order CPU architecture using renaming and reorder buffers.
• Hardware Synthesis Workflows - Provides a dedicated workflow for converting processor simulations into physical FPGA hardware prototypes.
• CPU Architectural Simulators - Ships a high-performance CPU simulator for architectural exploration and functional verification of processor execution.
• Hardware Description Frameworks - Provides a construction language for implementing high-performance hardware micro-architectures for rapid development.
• FPGA Hardware Design - Supports the transition of processor simulations into physical hardware prototypes using FPGA design workflows.
• Processor Prototypes - Translates processor simulations into synthesizable Verilog for deployment on FPGA hardware prototypes.
• Architectural Exploration Simulators - Includes a calibrated software simulator used for architectural exploration and development of processor designs.
• Instruction-Level Pipelining - Manages execution order using renaming and reorder buffers to exploit instruction-level parallelism.
• Hardware Branch Prediction - Forecasts branch outcomes and targets using tagged geometric history to minimize pipeline stalls.
• Out-of-Order Execution Architectures - Implements a superscalar out-of-order CPU architecture using renaming and reorder buffers for parallel execution.
• Out-of-Order Execution Engines - Builds superscalar engines with branch prediction and instruction scheduling to increase processing throughput.
• Hardware Construction Languages - Provides a construction-based framework using hardware construction languages to design and verify processor micro-architectures.
• Hardware Construction Languages - Provides a high-level hardware construction language to define micro-architectures and synthesize hardware code.
• Processor Execution Simulators - Provides a software environment for verifying hardware behavior by executing binary workloads prior to physical implementation.
• Hardware Core Verifications - Verifies processor core correctness by simulating binary workloads in a software environment before manufacturing.
• Hardware Cache Replacement Policies - Utilizes re-reference interval prediction for cache line eviction to maintain high hit rates.
• Re-reference Interval Prediction - Uses re-reference interval prediction (RRIP) for cache replacement to maintain higher hit rates than LRU.
• Non-blocking Caches - Implements a non-blocking cache hierarchy that tracks pending requests to prevent pipeline stalls during memory misses.
• Hardware Design Toolchains - Includes a dedicated hardware design toolchain for accelerating functional verification and performance evaluation.
• Pipeline and Cache Optimizations - Develops non-blocking caches and prefetching mechanisms to optimize pipeline and cache throughput.
• Verilog Generators - Generates synthesizable Verilog files from high-level hardware descriptions for logic synthesis.
• Geometric Branch Predictors - Implements tagged geometric branch prediction to minimize pipeline stalls in the instruction stream.
• Memory Dependency Predictors - Provides store-set memory dependency prediction to optimize the execution order of load and store operations.
• Hardware Arithmetic Units - Implements signed binary multiplication and division using optimized digit-recurrence and fast multiplier techniques.
• Hardware Data Prefetching - Reduces data access penalties via spatial memory streaming and stride or temporal prefetching patterns.
• Instruction Fetch Units - Provides a scalable front-end architecture designed to deliver instruction streams to the processor at high speeds.
• Instruction Prefetching - Loads instructions into the cache before they are explicitly requested to reduce fetch latency.
• Memory Banking Implementation - Implements hardware memory banking to allow simultaneous access to different memory locations and increase cache bandwidth.
• Memory Dependency Prediction - Analyzes store sets and wait tables to predict dependencies between memory operations and optimize execution order.
• Non-blocking Cache Architectures - Implements a memory system capable of handling multiple outstanding cache misses without stalling the pipeline.
• Coalesced Translation Lookaside Buffers - Implements coalesced translation lookaside buffers to optimize virtual-to-physical address translation.
• Page Table Translators - Implements virtual-to-physical address translation using coalesced large-reach translation lookaside buffers.
• Cache Banked Memory Optimizations - Enhances memory access speed through the implementation of multi-port banked data arrays.

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