clash-lang/clash-compiler
Clash Compiler
Clash is a functional hardware compiler and hardware description language compiler that translates strongly typed functional programs written in Haskell into synthesizable VHDL, Verilog, and SystemVerilog code. It serves as a development tool allowing digital designers to write hardware descriptions in functional languages and compile them directly to FPGA targets and physical netlists.
The compilation infrastructure covers structural hardware compilation, including graph-based code normalization, functional language translation, and netlist generation. It features type-level clock domain safety checks to enforce validation rules across multiple asynchronous clock frequencies, phases, and domain boundaries. Additional capabilities include interactive hardware evaluation interpreters for verifying logic behavior without external test benches, and stream-based sequential modeling for representing digital logic and feedback loops.
The system also provides compiler configuration utilities for command-line options and typechecker plugins, along with debugging tools for rewrite history inspection and terminal-based replay of optimization steps.
Features
- FPGA Hardware Design - Compiles strongly typed functional programs written in Haskell directly into target-ready VHDL, Verilog, and SystemVerilog code for physical FPGAs.
- Hardware-Targeted Compilation - Translates high-level functional source code into synthesizable low-level description code for hardware targets.
- Source Code Translations - Translates high-level functional programming language source code into standard hardware description languages.
- FPGA - Translates high-level functional algorithms into VHDL, Verilog, or SystemVerilog for targeting physical FPGA devices.
- Logic Design Simulations - Loads hardware descriptions directly into an interactive interpreter to verify component logic behavior without external test benches.
- Digital Circuit Construction - Models digital logic using infinite streams of values flowing through components to enable natural descriptions of feedback loops.
- Netlist Generation - Converts normalized core intermediate representations into structured structural descriptions of hardware parts, wires, and interconnections.
- Parametric Hardware Generators - Creates flexible digital components using higher-order functions combined with type inference to parameterize hardware generation.
- Clock Domain Conversion - Coordinates designs operating across different clock frequencies and phases by enforcing safety checks during clock domain crossings.
- Functional Programming Compilers - Transforms purely functional code into synthesizable netlists and hardware description language modules for digital circuit design.
- Hardware Description Languages - Translates high-level functional programs written in strongly typed languages into synthesizable VHDL, Verilog, and SystemVerilog code.
- Type-Safe Clock Domains - Enforces compile-time validation rules and safety checks across multiple asynchronous clock frequencies and phases.
- Graph Pattern Rewriters - Applies algebraic rewrite systems and transformation passes to reduce core expression graphs into standardized component forms.
- Normalization - Applies rewrite systems and transformation passes to reduce core expressions into standardized normal forms.
- Component-Based Sequential Processing - Represents digital logic and feedback loops using continuous streams of values flowing through discrete time-stepped components.
- Interactive Read-Eval-Print Loops - Loads compiled hardware component descriptions into an interactive evaluation loop to verify logic behavior.
- Higher Order Function Implementation - Transforms functional language constructs and type inference engines into synthesizable digital logic netlists.
- Haskell Resources - Designs synthesizable digital hardware using strong functional programming concepts and rich type systems from Haskell.
- Interactive Logic Testing - Verifies digital logic behavior directly inside an interactive interpreter environment without external test benches.
Star history
How this analysis was created: This summary and feature list were written by an AI model that read the project's README and public documentation pages. Each feature links to the documentation it came from; stars, license and language come straight from the GitHub API. The model does not read the source code, and the analysis is refreshed when the project is re-analysed. Learn more on our About page.
