ghdl/ghdl
Ghdl
GHDL is a compiler and simulator for VHDL hardware descriptions. It functions as a multi-pass analysis elaborator that resolves design hierarchies and dependencies to prepare hardware descriptions for simulation or synthesis.
The project transforms VHDL source code into executable binaries for high-speed digital design verification and serves as a synthesis tool that converts descriptions into structural netlists compatible with vendor or open-source flows. It also implements the Language Server Protocol to provide static analysis, autocomplete, and code navigation for VHDL files.
The toolset covers hardware verification and monitoring through code coverage collection, PSL verification reporting, and the export of signal waveforms for external visualization. It further supports hardware co-simulation by providing a C-based foreign function interface to connect simulations with external software libraries and verification frameworks.
Features
- Hardware Simulation - Provides a complete environment for analyzing and simulating digital hardware descriptions.
- Co-Simulation Interfaces - Provides a C-based foreign function interface to connect VHDL simulations with external software libraries.
- FPGA Hardware Design - Transforms complex VHDL descriptions into synthesizable components for FPGA hardware design.
- HDL Logic Synthesis - Synthesizes VHDL descriptions into gate-level netlists compatible with hardware implementation tools.
- Logic Synthesis Tools - Converts VHDL descriptions into structural netlists compatible with vendor or open-source synthesis flows.
- Multi-Pass Compiler Pipelines - Uses a multi-pass compiler architecture to resolve design hierarchies and dependencies for simulation.
- Binary Compilers - Converts VHDL source code into native binary executables to significantly increase simulation execution speed.
- Simulation Binary Generation - Compiles high-level VHDL descriptions into standalone executable binaries for high-speed simulation.
- Hardware Core Verifications - Ensures VHDL designs meet specifications through the use of assertions and code coverage tools.
- Procedural Interfaces - Allows interaction with external applications during simulation through standard procedural interfaces.
- Language Servers - Implements a Language Server that provides IDE features like autocompletion and diagnostics for VHDL.
- LSP-Based Code Analysis - Uses the Language Server Protocol to provide real-time static analysis, autocomplete, and code navigation.
- Constrained Random Verification - Provides integration with external libraries to perform constrained random verification on hardware designs.
- Hardware Co-Simulation Interfaces - Enables co-simulation of VHDL designs with external languages for signal inspection and callback triggering.
- Simulation Waveform Exports - Exports signal activity and timing data into standard formats for visualization in external waveform viewers.
- Cycle-Accurate Emulators - Implements delta-cycle event scheduling to provide precise, cycle-accurate simulation of concurrent hardware behavior.
- Foreign Function Interfaces - Provides a C-based foreign function interface to enable interoperability between simulation kernels and external libraries.
- Intermediate Representations - Implements backend-agnostic intermediate representations to support multiple target machine-code generators.
- Code Coverage Analysis - Tracks which parts of the hardware description are exercised during simulation to provide code coverage metrics.
- Assertion Verification Reports - Produces detailed reports on passed, failed, or uncovered PSL assertions after simulation completion.
- Simulation and Modeling - VHDL simulator for hardware design.
Star history
How this analysis was created: This summary and feature list were written by an AI model that read the project's README and public documentation pages. Each feature links to the documentation it came from; stars, license and language come straight from the GitHub API. The model does not read the source code, and the analysis is refreshed when the project is re-analysed. Learn more on our About page.
