GHDL is a compiler and simulator for VHDL hardware descriptions. It functions as a multi-pass analysis elaborator that resolves design hierarchies and dependencies to prepare hardware descriptions for simulation or synthesis.
The project transforms VHDL source code into executable binaries for high-speed digital design verification and serves as a synthesis tool that converts descriptions into structural netlists compatible with vendor or open-source flows. It also implements the Language Server Protocol to provide static analysis, autocomplete, and code navigation for VHDL files.
The toolset covers hardware verification and monitoring through code coverage collection, PSL verification reporting, and the export of signal waveforms for external visualization. It further supports hardware co-simulation by providing a C-based foreign function interface to connect simulations with external software libraries and verification frameworks.