digital logic design curriculum / educational resources

This project consists of technical instructional guides and a structured computer science curriculum designed to teach the construction of a full computing stack from transistors up to a web browser. It provides a 12-week educational course that covers the fundamental domains of computer architecture and digital logic design. The curriculum is distinguished by its first-principles approach, guiding the learner through the engineering of CPUs, FPGAs, and PCBs using digital logic and hardware description languages. It includes specific syllabi for building a hardware design, a TCP/IP network st

Logisim Evolution is a digital logic simulator and schematic editor used for designing and verifying digital circuits. It functions as a tool for digital circuit design and real-time logic simulation, allowing users to create schematic representations of electronic hardware using gates and registers. The software distinguishes itself by providing hardware description language tools that allow for the definition of custom component behavior and the translation of visual schematics into synthesis-ready code for FPGA hardware deployment. It also serves as a bridge for physical hardware integrati

Books-Free-Books is an academic content aggregator and search engine designed to locate and retrieve open-source books and educational materials. It functions as a digital library discovery tool that unifies disparate open-access databases into a single searchable index, providing students and educators with a centralized platform for accessing peer-reviewed literature and scholarly resources. The platform distinguishes itself by aggregating data from multiple remote sources and normalizing these disparate structures into a cohesive interface. It utilizes URL-based state persistence, which en

Bitwise is a computer architecture education kit and a comprehensive set of guides for building a custom CPU, operating system, and compiler from scratch. It serves as a CPU design tutorial and a practical framework for implementing a unique instruction set architecture. The project provides a custom instruction set architecture toolchain, including resources for creating a matching assembler and compiler. It further includes a hardware development guide for synthesizing computer components and peripheral controllers for deployment on programmable logic devices and FPGAs. The kit covers full

Chisel is a hardware construction language and description tool used to define digital circuits. It functions as a generator that converts high-level hardware descriptions into synthesizable Verilog code for use in ASIC and FPGA design. The project enables the creation of parameterizable hardware templates and reusable digital components. It leverages functional and object-oriented programming patterns to transform complex circuit representations into finalized hardware descriptions. The toolset covers the register-transfer level design workflow, allowing users to model digital circuits usin

GHDL is a compiler and simulator for VHDL hardware descriptions. It functions as a multi-pass analysis elaborator that resolves design hierarchies and dependencies to prepare hardware descriptions for simulation or synthesis. The project transforms VHDL source code into executable binaries for high-speed digital design verification and serves as a synthesis tool that converts descriptions into structural netlists compatible with vendor or open-source flows. It also implements the Language Server Protocol to provide static analysis, autocomplete, and code navigation for VHDL files. The toolse

Digital is a digital logic circuit simulator and hardware design verification tool. It provides a visual environment for designing, testing, and verifying electronic circuits using event-based simulation and automated logic synthesis. The platform functions as a logic synthesis tool that applies boolean algebra to minimize gate configurations and convert truth tables into efficient hardware. It also serves as an HDL export tool, translating visual circuit graphs into VHDL or Verilog code, and as a CPLD deployment tool that generates JEDEC files for flashing programmable logic chips. The soft

This project is a centralized repository and academic resource aggregator designed to guide students through a structured computer science curriculum. It provides a comprehensive roadmap of foundational courses and technical materials, helping learners navigate the transition from introductory programming to advanced software engineering proficiency. The repository distinguishes itself through a community-driven approach, where study paths and resource collections are refined and expanded via peer feedback and collaborative contributions. By organizing high-quality lecture notes, assignments,

XiangShan is a high-performance RISC-V processor core and a hardware description language framework. It provides a construction-based system for designing, simulating, and verifying complex processor micro-architectures and peripheral devices. The project includes a high-performance CPU simulator used for architectural exploration and functional verification of processor execution. The project implements a superscalar out-of-order CPU architecture that uses renaming and reorder buffers to execute instructions in parallel. It generates synthesizable Verilog files from hardware descriptions to

The Powder Toy is a physics sandbox simulator and programmable logic simulator. It provides a real-time environment for modeling the interactions of solids, liquids, and gases using a particle physics engine that calculates movement, heat transfer, and pressure on a 2D grid. The system is a scriptable simulation environment that supports custom plugins and scripting to automate workflows. It allows for the construction of functional electronic circuits and complex machines using integrated materials and conductive elements. The software covers environmental dynamics modeling and material int

Algorithmica is an open-access knowledge base and computer science textbook designed for the publication of structured instructional materials. It functions as an educational content management system and a collaborative documentation site for hosting technical knowledge and course drafts for public consumption. The platform enables collaborative technical writing and authoring through version control and web editors, utilizing an automated pipeline to generate previews of pending changes. The system manages large collections of learning materials using static site generation, markdown-drive

picorv32 is a size-optimized RISC-V CPU core and synthesizable processor IP designed for integration into FPGA and ASIC hardware designs. It serves as an open-source CPU architecture and embedded system-on-chip component that implements a standard RISC-V instruction set. The design features a modular architecture that allows for the integration of external coprocessors to implement custom non-branching instructions. It includes a parameterized integer unit with configurable multiplication and division cores to balance performance against total logic gate count. The project covers a broad ran