Computer Architecture and CPU Design
Educational resources, simulators, and documentation for understanding processor architecture, instruction sets, and hardware design principles.
Computer Architecture and CPU Design
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- pervognsen/bitwise
pervognsen/bitwise
5,250View on GitHubBitwise is a computer architecture education kit and a comprehensive set of guides for building a custom CPU, operating system, and compiler from scratch. It serves as a CPU design tutorial and a practical framework for implementing a unique instruction set architecture. The project provides a custom instruction set architecture toolchain, including resources for creating a matching assembler and compiler. It further includes a hardware development guide for synthesizing computer components and peripheral controllers for deployment on programmable logic devices and FPGAs. The kit covers full-stack systems engineering, spanning hardware emulation development, operating system implementation with task switching, and the creation of custom compiler toolchains. It includes instructions for building a complete computer system, from the initial hardware logic to the final software stack.
This project provides a comprehensive educational framework for designing custom CPU architectures, including the necessary toolchains for assembly and compiler development alongside hardware synthesis guides for FPGAs.
CHDL Logic Synthesis - verilator/verilator
verilator/verilator
3,365View on GitHubVerilator is a hardware simulation engine and toolchain that translates Verilog and SystemVerilog hardware description languages into optimized C++ or SystemC models. It functions as a compiler and transpiler, converting hardware designs into executable binaries to achieve high-speed simulation and integration into software environments. The project distinguishes itself by focusing on simulation acceleration through the generation of optimized C++ classes and cycle-accurate models. It provides a SystemVerilog linter for static analysis of hardware designs and a hardware coverage analyzer to track functional and code coverage during the verification process. The system covers a broad range of capabilities including hardware-software co-simulation via Direct Programming Interfaces and the serialization of signal activity into waveform trace files. It supports multi-threaded model execution, hierarchical verilation for large designs, and performance profiling to identify execution bottlenecks. The toolchain allows for custom build configuration, including cross-compilation and containerized execution, and provides mechanisms for custom code injection into generated models.
Verilator is a professional-grade hardware simulation toolchain that translates Verilog and SystemVerilog into executable models, providing the core infrastructure needed to simulate and verify complex processor architectures.
SystemVerilogHDL CompilersHDL Design Linting - ffmpeg/asm-lessons
FFmpeg/asm-lessons
12,067View on GitHubThis project serves as an educational resource for learning and implementing low-level assembly language optimizations. It provides a structured guide for developers to master hardware-specific instructions and manual performance tuning, focusing on the translation of high-level code into efficient machine-level operations for resource-constrained environments. The materials emphasize techniques for maximizing computational throughput in multimedia processing. By covering instruction-level parallelism, register management, and data parallelism, the project enables the development of software that utilizes modern processor capabilities to accelerate audio and video data processing. The curriculum addresses fundamental processor operations and the application of specialized assembly techniques. It covers core concepts such as cache-aware memory access, instruction-level pipelining, loop unrolling, and branch optimization to help developers meet strict performance requirements in demanding systems.
This project provides educational tutorials and guides on assembly optimization and low-level performance tuning rather than a simulator or hardware design tool for visualizing processor architecture.
Instruction Set Architecture LearningInstruction Set Architecture References - chipsalliance/chisel
chipsalliance/chisel
4,691View on GitHubChisel is a hardware construction language and description tool used to define digital circuits. It functions as a generator that converts high-level hardware descriptions into synthesizable Verilog code for use in ASIC and FPGA design. The project enables the creation of parameterizable hardware templates and reusable digital components. It leverages functional and object-oriented programming patterns to transform complex circuit representations into finalized hardware descriptions. The toolset covers the register-transfer level design workflow, allowing users to model digital circuits using typed primitives for signals, registers, and wires. It also includes a verification environment for simulating circuit behavior by driving inputs and stepping the clock to validate hardware logic.
Chisel is a hardware construction language that allows you to design and simulate digital circuits at the register-transfer level, providing a powerful, code-driven approach to learning and implementing hardware architecture.
ScalaVerilog Generators - ghdl/ghdl
ghdl/ghdl
2,759View on GitHubGHDL is a compiler and simulator for VHDL hardware descriptions. It functions as a multi-pass analysis elaborator that resolves design hierarchies and dependencies to prepare hardware descriptions for simulation or synthesis. The project transforms VHDL source code into executable binaries for high-speed digital design verification and serves as a synthesis tool that converts descriptions into structural netlists compatible with vendor or open-source flows. It also implements the Language Server Protocol to provide static analysis, autocomplete, and code navigation for VHDL files. The toolset covers hardware verification and monitoring through code coverage collection, PSL verification reporting, and the export of signal waveforms for external visualization. It further supports hardware co-simulation by providing a C-based foreign function interface to connect simulations with external software libraries and verification frameworks.
This is a professional-grade VHDL compiler and simulator that allows you to model and verify hardware architectures at the register-transfer level, providing the core simulation engine needed to study processor design and logic behavior.
VHDLHDL Logic Synthesis - cnrv/riscv-soc-book
cnrv/riscv-soc-book
This project provides a comprehensive educational guide and practical implementation examples for building a RISC-V processor, serving as a hands-on resource for understanding hardware architecture and instruction set design.
Computer Architecture
