InkboxSoftware/excelCPU

This project is a web-based educational environment designed to simulate 8-bit processor architecture and assembly language execution. It functions as a virtual machine that translates symbolic assembly code into machine instructions, allowing users to observe the fetch-decode-execute cycle and its impact on system state in real time. The simulator distinguishes itself through a reactive interface that binds visual register and memory displays directly to the underlying processor state. It incorporates a two-pass assembler that manages symbolic label resolution and memory address mapping, pro

XiangShan is a high-performance RISC-V processor core and a hardware description language framework. It provides a construction-based system for designing, simulating, and verifying complex processor micro-architectures and peripheral devices. The project includes a high-performance CPU simulator used for architectural exploration and functional verification of processor execution. The project implements a superscalar out-of-order CPU architecture that uses renaming and reorder buffers to execute instructions in parallel. It generates synthesizable Verilog files from hardware descriptions to

This project is a multilingual educational framework that provides curated roadmaps and translated resources for mastering core computer science subjects. It serves as a Chinese translation of a structured guide designed to help students and engineers learn computer science fundamentals through a sequence of recommended books and courses. The framework focuses on technical content localization, converting English computer science roadmaps into Chinese to improve accessibility. It utilizes a manual translation workflow to ensure conceptual accuracy across its study guides and resource collecti

Digital-Logic-Sim is a digital logic simulator and interactive circuit designer used for building and simulating digital hardware circuits. It functions as a visual editor and logic state visualizer that allows for the creation of complex digital logic models using logic gates, wires, and custom chips. The system includes a custom logic chip builder, enabling the grouping of basic logic gates into reusable components to create layered hardware architectures. Users can monitor these designs through a logic state visualizer that displays signal states and memory values using light indicators an