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excelCPU is a spreadsheet-based computer emulator that simulates a 16-bit central processing unit. It functions as an educational CPU model where the system state, registers, and random access memory are managed within a grid of spreadsheet cells.
The main features of inkboxsoftware/excelcpu are: Computer Architecture, Assemblers, Cell-Based State Storage, CPU Architectural Simulators, Spreadsheet-Based CPU Simulators, CPU Architectures, Spreadsheet-Based Emulators, Custom Assembly Programming.
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This project is a web-based educational environment designed to simulate 8-bit processor architecture and assembly language execution. It functions as a virtual machine that translates symbolic assembly code into machine instructions, allowing users to observe the fetch-decode-execute cycle and its impact on system state in real time. The simulator distinguishes itself through a reactive interface that binds visual register and memory displays directly to the underlying processor state. It incorporates a two-pass assembler that manages symbolic label resolution and memory address mapping, pro
XiangShan is a high-performance RISC-V processor core and a hardware description language framework. It provides a construction-based system for designing, simulating, and verifying complex processor micro-architectures and peripheral devices. The project includes a high-performance CPU simulator used for architectural exploration and functional verification of processor execution. The project implements a superscalar out-of-order CPU architecture that uses renaming and reorder buffers to execute instructions in parallel. It generates synthesizable Verilog files from hardware descriptions to
Computerraria is a digital logic circuit simulator and computer architecture educational tool. It provides a sandbox environment for building and testing functional computer systems by connecting modular logic gates and electronic wires. The project serves as a RISC-V architecture simulator that executes RV32I machine code using virtualized hardware components. It includes a virtualized CPU toolchain that uses containerized systems to compile source code into binary formats compatible with these custom processor architectures. The system covers digital logic circuit design and RISC-V ISA sim
This project is a multilingual educational framework that provides curated roadmaps and translated resources for mastering core computer science subjects. It serves as a Chinese translation of a structured guide designed to help students and engineers learn computer science fundamentals through a sequence of recommended books and courses. The framework focuses on technical content localization, converting English computer science roadmaps into Chinese to improve accessibility. It utilizes a manual translation workflow to ensure conceptual accuracy across its study guides and resource collecti