Schweigi/assembler-simulator
Assembler Simulator
This project is a web-based educational environment designed to simulate 8-bit processor architecture and assembly language execution. It functions as a virtual machine that translates symbolic assembly code into machine instructions, allowing users to observe the fetch-decode-execute cycle and its impact on system state in real time.
The simulator distinguishes itself through a reactive interface that binds visual register and memory displays directly to the underlying processor state. It incorporates a two-pass assembler that manages symbolic label resolution and memory address mapping, providing a structured way to organize and navigate assembly programs. Users can control the clock frequency of the virtual processor, enabling them to pace instruction execution for detailed observation and debugging.
The application provides a comprehensive suite of tools for monitoring internal processor flags, register values, and memory contents. It supports flexible data formatting for memory and registers, allowing values to be viewed in either hexadecimal or decimal notation. The environment is built as a browser-based application, facilitating the study of low-level computing concepts and embedded systems logic without requiring external hardware.
Features
- CPU Architectural Simulators - Simulates an 8-bit CPU architecture with general-purpose registers and memory for educational purposes.
- Assembly Simulation - Acts as a web-based educational tool for simulating assembly language execution on a virtual processor.
- Assemblers - Translates assembly language source code into machine-executable operations for browser-based testing.
- Computer Architecture Curricula - Facilitates learning of processor architecture through real-time visualization of assembly execution.
- Fetch-Execute Cycles - Implements a fetch-decode-execute loop to simulate the core operation of a processor.
- Two-Pass - Translates symbolic assembly code into machine instructions using a two-pass process for label resolution.
- Assembly Language IDEs - Enables step-by-step execution and analysis of assembly code to identify logic errors.
- Execution State Monitoring - Provides real-time monitoring of registers, memory contents, and internal processor flags.
- Clock-Controlled Execution - Provides a timer-based clock mechanism to regulate the speed of instruction execution during simulation.
- Execution Speed Controls - Allows users to adjust the clock frequency of the virtual processor to control execution speed.
- Eight-Bit Component Simulators - Simulates 8-bit processor architectures to verify program flow and debug logic.
- Low-Level Systems Programming - Provides an environment for practicing low-level programming by writing and testing assembly code.
- Low-Level Debuggers - Functions as a virtual machine environment for real-time debugging and processor state monitoring.
- Virtual Memory Mapping - Manages a linear array of bytes as simulated system memory for direct addressing and label resolution.
- Symbol-To-Address Mapping - Maps symbolic labels to specific memory locations to improve code organization and readability.
- Reactive State Bindings - Synchronizes visual register and memory displays with the processor state using reactive data-binding.
Star history
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