YosysHQ/picorv32
Picorv32
picorv32 is a size-optimized RISC-V CPU core and synthesizable processor IP designed for integration into FPGA and ASIC hardware designs. It serves as an open-source CPU architecture and embedded system-on-chip component that implements a standard RISC-V instruction set.
The design features a modular architecture that allows for the integration of external coprocessors to implement custom non-branching instructions. It includes a parameterized integer unit with configurable multiplication and division cores to balance performance against total logic gate count.
The project covers a broad range of hardware development capabilities, including memory-mapped flash execution, interrupt management, and valid-ready bus interfaces for memory and peripheral synchronization. It also provides tools for hardware verification through simulation, execution flow tracing, and the generation of SMT2 models for formal mathematical verification of CPU logic.
Features
- Custom CPU Architecture Design - Implements a modular, open-source RISC-V CPU architecture with configurable integer units and coprocessor interfaces.
- RISC-V CPU Cores - Implements a size-optimized RISC-V CPU core designed for integration into FPGA and ASIC hardware.
- RISC-V Processor Cores - Provides a size-optimized RISC-V processor core suitable for synthesis in FPGA and ASIC designs.
- Embedded SoC Components - Provides a processor core with integrated memory controllers and UART interfaces for minimal system-on-chip designs.
- Hardware Logic Descriptions - Delivers a hardware description designed for conversion into logic netlists via synthesis tools.
- RISC-V ISA Implementations - Implements a standard RISC-V instruction set with configurable support for various architectural variants.
- RTL Design - Provides a synthesizable hardware description of the processor core at the register-transfer level.
- Synthesizable CPU Cores - Provides a size-optimized hardware core suitable for physical chip integration to run standard instruction sets.
- In-Place Execution from Flash - Allows the processor to execute firmware directly from mapped SPI flash memory without copying to RAM.
- Firmware Debugging - Executes code from memory and traces instruction flow to debug embedded software.
- Virtual Hardware Simulators - Runs instructions in a virtual environment to verify logic correctness before physical FPGA or ASIC implementation.
- Interrupt Handlers - Manages the hardware transition to interrupt handlers by saving registers and jumping to service routines.
- Digital Logic Verification - Runs simulation testbenches and formal models to ensure digital logic correctness before fabrication.
- FPGA Hardware Design - Combines a processor core with memory and UART controllers for synthesis on field-programmable gate arrays.
- Integer Arithmetic Units - Computes multiplication and division using internal cores with options for area optimization or single-cycle speed.
- Memory Bus Interfaces - Implements a standard valid-ready interface for synchronized instruction fetches and data transfers between the core and memory.
- Parameterized Integer Units - Includes configurable multiplication and division cores to balance execution speed against total logic gate count.
- Minimal SoC Designs - Creates simple system-on-chip designs with integrated memory controllers and UART for hardware control.
- Handshake Bus Interfaces - Manages memory fetches and data transfers using a valid-ready handshake protocol for synchronization.
- Interrupt Controllers - Features a built-in controller that manages multiple interrupt inputs, including masking and request handling.
- CPU - Implements a built-in controller that manages hardware request signals and transitions to service routines.
- Coprocessor Interfaces - Provides a modular interface for integrating external hardware modules to implement custom non-branching instructions.
- Custom Instruction Extensions - Adds specialized co-processors and custom non-branching instructions to the processor core.
- ISA Extension Interfaces - Enables the integration of external co-processors via a dedicated interface for specialized non-branching instructions.
- Instruction Tracing - Streams internal signal transitions and instruction sequences to files for post-simulation debugging.
- Execution Tracing - Captures and logs the sequence of executed instructions to files for post-simulation analysis.
- Hardware Performance Benchmarking - Includes testbenches and standard benchmarks to calculate processing speed and verify hardware correctness.
- Hardware Core Verifications - Runs testbenches and firmware checks through simulators to ensure the processor core behaves correctly.
- Hardware Logic Models - Generates SMT2 models to allow for the mathematical verification of CPU logic and instruction correctness.
- Hardware Logic Verification - Generates SMT2 models to mathematically prove the correctness of the CPU logic using formal solvers.
- SMT2 Model Generation - Converts hardware descriptions into mathematical formats to verify design correctness using formal logic tools.
