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2 dépôts

Awesome GitHub RepositoriesInteger Arithmetic Units

Hardware implementations of integer multiplication and division within a processor core.

Distinct from Integer Arithmetic: Focuses on synthesized hardware arithmetic logic rather than software libraries or pointer math.

Explore 2 awesome GitHub repositories matching hardware & iot · Integer Arithmetic Units. Refine with filters or upvote what's useful.

Awesome Integer Arithmetic Units GitHub Repositories

Trouvez les meilleurs dépôts grâce à l'IA.Nous recherchons les dépôts les plus pertinents grâce à l'IA.
  • infrasys-ai/aisystemAvatar de Infrasys-AI

    Infrasys-AI/AISystem

    17,017Voir sur GitHub↗

    AISystem is a comprehensive AI full-stack infrastructure project covering the entire pipeline from AI chip architecture to high-level training frameworks. It encompasses the development of AI compiler frameworks, inference engines, and distributed training orchestrators designed to coordinate workloads across a heterogeneous compute stack of CPUs, GPUs, and NPUs. The project focuses on the deep integration of software and hardware, employing software-hardware co-design to align tensor layouts with physical memory structures. It provides specialized capabilities for accelerating Transformer mo

    Implements low-level arithmetic and logic operations within the processor core for integer and bitwise calculations.

    Jupyter Notebookaiaiinfraaisys
    Voir sur GitHub↗17,017
  • yosyshq/picorv32Avatar de YosysHQ

    YosysHQ/picorv32

    4,222Voir sur GitHub↗

    picorv32 is a size-optimized RISC-V CPU core and synthesizable processor IP designed for integration into FPGA and ASIC hardware designs. It serves as an open-source CPU architecture and embedded system-on-chip component that implements a standard RISC-V instruction set. The design features a modular architecture that allows for the integration of external coprocessors to implement custom non-branching instructions. It includes a parameterized integer unit with configurable multiplication and division cores to balance performance against total logic gate count. The project covers a broad ran

    Computes multiplication and division using internal cores with options for area optimization or single-cycle speed.

    Verilog
    Voir sur GitHub↗4,222
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