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6 dépôts

Awesome GitHub RepositoriesMemory Access Pattern Optimizers

Optimizes memory access patterns through layout annotations, cache swizzling, and pipelining for compute kernels.

Distinct from Tiled Memory Access Patterns: Distinct from Tiled Memory Access Patterns: focuses on applying optimizations (swizzling, pipelining) to access patterns, not just describing the patterns.

Explore 6 awesome GitHub repositories matching software engineering & architecture · Memory Access Pattern Optimizers. Refine with filters or upvote what's useful.

Awesome Memory Access Pattern Optimizers GitHub Repositories

Trouvez les meilleurs dépôts grâce à l'IA.Nous recherchons les dépôts les plus pertinents grâce à l'IA.
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    AISystem is a comprehensive AI full-stack infrastructure project covering the entire pipeline from AI chip architecture to high-level training frameworks. It encompasses the development of AI compiler frameworks, inference engines, and distributed training orchestrators designed to coordinate workloads across a heterogeneous compute stack of CPUs, GPUs, and NPUs. The project focuses on the deep integration of software and hardware, employing software-hardware co-design to align tensor layouts with physical memory structures. It provides specialized capabilities for accelerating Transformer mo

    Uses high-bandwidth memory and on-chip buffers to reduce movement latency and minimize external memory access for large parameters.

    Jupyter Notebookaiaiinfraaisys
    Voir sur GitHub↗17,017
  • federico-busato/modern-cpp-programmingAvatar de federico-busato

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    This project is a comprehensive educational resource and programming course covering C++ language semantics and features from C++03 through C++26. It provides structured tutorials and technical guides focused on modern C++ development. The material offers specialized instruction on template metaprogramming, including the use of type traits and compile-time computations. It features detailed guides on concurrency and parallelism for multi-core execution, as well as a reference for software design applying SOLID principles and RAII. Additionally, it covers build performance optimization to redu

    Covers optimization of memory access patterns to maximize CPU cache efficiency and minimize latency.

    HTMLc-plus-pluscode-qualitycompilers
    Voir sur GitHub↗15,808
  • openxiangshan/xiangshanAvatar de OpenXiangShan

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    7,081Voir sur GitHub↗

    XiangShan is a high-performance RISC-V processor core and a hardware description language framework. It provides a construction-based system for designing, simulating, and verifying complex processor micro-architectures and peripheral devices. The project includes a high-performance CPU simulator used for architectural exploration and functional verification of processor execution. The project implements a superscalar out-of-order CPU architecture that uses renaming and reorder buffers to execute instructions in parallel. It generates synthesizable Verilog files from hardware descriptions to

    Enhances memory access speed through the implementation of multi-port banked data arrays.

    Scalachiselmicroarchitecturerisc-v
    Voir sur GitHub↗7,081
  • flashlight/flashlightAvatar de flashlight

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    5,443Voir sur GitHub↗

    Flashlight est une bibliothèque de machine learning et de tenseurs autonome en C++ utilisée pour construire et entraîner des réseaux de neurones. Elle fonctionne comme un framework complet de réseaux de neurones et un moteur de différenciation automatique, fournissant les outils pour construire des graphes de calcul et calculer les gradients via la rétropropagation. Le projet sert de framework d'entraînement distribué, utilisant des opérations all-reduce pour synchroniser les gradients et les paramètres sur plusieurs nœuds de calcul et appareils. Il se distingue par une intégration profonde de la manipulation de tenseurs haute performance, l'interopérabilité native de la mémoire des appareils et un système pour synchroniser les poids entre les workers distribués afin d'accélérer l'entraînement de modèles à grande échelle. Le framework couvre un large éventail de capacités de deep learning, incluant la composition modulaire de couches pour concevoir des architectures complexes comme des blocs résiduels et des cellules récurrentes. Il fournit des utilitaires étendus de gestion de données pour l'ingestion et le préchargement, ainsi que des systèmes de sérialisation pour persister les états de modèle. De plus, il inclut une suite d'outils de surveillance et d'observabilité pour suivre les métriques d'entraînement et mesurer les erreurs de séquence. La bibliothèque est implémentée en C++.

    Reduces memory allocations and improves performance by fusing multiple function calls into a single kernel call.

    C++
    Voir sur GitHub↗5,443
  • tile-ai/tilelangAvatar de tile-ai

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    5,226Voir sur GitHub↗

    TileLang is a Python-embedded domain-specific language compiler that JIT-compiles and autotunes GPU kernels. It uses a tile-based DSL, automatic software pipelining, and parallel autotuning to generate optimized GPU kernels at runtime. It supports tensor core operations with Pythonic syntax, automatic memory management, and thread mapping. The compiler searches over tile sizes, thread counts, and scheduling policies, compiling and benchmarking candidates in parallel to find the fastest kernel. It also caches compiled binaries and tuning results to disk for reuse across sessions. TileLang inc

    Optimizes memory access patterns using layout annotations, swizzling, and pipelining for GPU kernels.

    Python
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  • dendibakh/perf-ninjaAvatar de dendibakh

    dendibakh/perf-ninja

    3,754Voir sur GitHub↗

    perf-ninja is a collection of educational resources and curricula focused on CPU architecture, memory hierarchies, SIMD programming, and low-level performance engineering. It provides instructional material and practical labs for identifying and fixing CPU bottlenecks, such as cache misses and branch mispredictions. The project differentiates itself through specialized training in hardware-level optimizations, including the use of compiler intrinsics for SIMD vectorization and the implementation of branchless predicate execution to eliminate pipeline stalls. It also covers advanced binary-lev

    Provides techniques for rearranging loop iterations to ensure contiguous memory traversal and improve cache efficiency.

    C++
    Voir sur GitHub↗3,754
  1. Home
  2. Software Engineering & Architecture
  3. Shared Memory Management
  4. Memory Access Profilers
  5. Tiled Memory Access Patterns
  6. Memory Access Pattern Optimizers

Explorer les sous-tags

  • Bandwidth Maximization1 sous-tagTechniques using high-bandwidth memory and on-chip buffers to reduce data movement latency. **Distinct from Memory Access Pattern Optimizers:** Distinct from Memory Access Pattern Optimizers: focuses on the hardware resource utilization (HBM, on-chip buffers) to reduce latency rather than just the software access pattern
  • Kernel Call FusionOptimizations that combine multiple small function calls into a single kernel execution to reduce memory overhead. **Distinct from Memory Access Pattern Optimizers:** Focuses on fusing calls into a single kernel to reduce allocations, whereas memory access pattern optimizers focus on layout and swizzling.