27 dépôts
Utilities for examining memory allocation patterns and cache-line sharing to detect performance bottlenecks.
Distinct from Shared Memory Management: Distinct from Shared Memory Management: focuses on performance profiling and analysis of memory access rather than inter-process synchronization.
Explore 27 awesome GitHub repositories matching software engineering & architecture · Memory Access Profilers. Refine with filters or upvote what's useful.
simdjson is a high-performance JSON parser that utilizes SIMD instructions to process gigabytes of data per second. It functions as a SIMD JSON parser, a multithreaded NDJSON processing library, a UTF-8 validation engine, and a tool for JSON minification and string building. The project focuses on high-throughput data processing, enabling the ingestion of massive JSON volumes and the verification of UTF-8 encoding standards. It includes dedicated capabilities for constructing JSON strings with optimized memory usage and removing unnecessary whitespace from documents to reduce file size. The
Allocates extra space at the end of buffers to allow wide SIMD loads without memory access violations.
Triton is a parallel computing framework and high-level programming language designed for writing custom compute kernels. It functions as a deep learning compiler, translating complex mathematical operations into high-throughput instructions that maximize hardware utilization and memory efficiency on graphics processing units. The framework distinguishes itself through a hardware-agnostic compute abstraction that allows developers to define kernels without manual low-level tuning. It employs just-in-time compilation to generate optimized binary instructions at runtime, utilizing static data f
Organizes data movement into structured blocks to maximize cache locality and minimize latency.
FlameGraph is a performance profiling and visualization toolkit designed to identify bottlenecks in software execution. It functions as a processing engine that transforms raw stack trace samples into interactive, hierarchical diagrams. By representing aggregated execution frequency as nested rectangles, the tool allows developers to visualize hot code paths and analyze system behavior across both kernel and user-space environments. The project distinguishes itself through its ability to perform differential profile analysis, which highlights performance regressions or improvements by compari
Examines memory allocation patterns and cache-line sharing to detect performance issues related to memory usage.
The Disruptor is a lock-free inter-thread messaging library and high-performance event bus. It implements a concurrent ring buffer designed for high-concurrency and low-latency message sequencing. The project utilizes a specific messaging architecture to eliminate lock contention, enabling high-throughput event routing and the exchange of continuous event streams between threads. It ensures strict first-in-first-out ordering and immediate data visibility across processing threads. The library provides capabilities for lock-free data streaming, sequential data ordering, and sequence-based eve
Implements cache-line padding to eliminate false sharing and maximize CPU cache efficiency.
TinyGo is a specialized compiler and development toolkit designed to bring the Go programming language to resource-constrained microcontrollers and WebAssembly environments. It provides a bare-metal runtime environment that enables high-level code execution without the need for a traditional operating system, utilizing an LLVM-based backend to generate efficient machine instructions. The project distinguishes itself through aggressive optimization techniques tailored for small hardware, including a static memory allocation strategy and whole-program dead code elimination that significantly re
Ensures safe interaction with hardware registers by bypassing compiler optimizations for volatile memory access.
AISystem is a comprehensive AI full-stack infrastructure project covering the entire pipeline from AI chip architecture to high-level training frameworks. It encompasses the development of AI compiler frameworks, inference engines, and distributed training orchestrators designed to coordinate workloads across a heterogeneous compute stack of CPUs, GPUs, and NPUs. The project focuses on the deep integration of software and hardware, employing software-hardware co-design to align tensor layouts with physical memory structures. It provides specialized capabilities for accelerating Transformer mo
Uses high-bandwidth memory and on-chip buffers to reduce movement latency and minimize external memory access for large parameters.
This project is a comprehensive educational resource and programming course covering C++ language semantics and features from C++03 through C++26. It provides structured tutorials and technical guides focused on modern C++ development. The material offers specialized instruction on template metaprogramming, including the use of type traits and compile-time computations. It features detailed guides on concurrency and parallelism for multi-core execution, as well as a reference for software design applying SOLID principles and RAII. Additionally, it covers build performance optimization to redu
Covers optimization of memory access patterns to maximize CPU cache efficiency and minimize latency.
This project serves as an educational resource for learning and implementing low-level assembly language optimizations. It provides a structured guide for developers to master hardware-specific instructions and manual performance tuning, focusing on the translation of high-level code into efficient machine-level operations for resource-constrained environments. The materials emphasize techniques for maximizing computational throughput in multimedia processing. By covering instruction-level parallelism, register management, and data parallelism, the project enables the development of software
Aligns data structures and access patterns to hardware cache lines to prevent performance degradation from frequent main memory fetches.
This project is a collection of educational resources and technical guides focused on Go performance optimization. It provides instruction on improving execution speed and reducing memory usage through code and architectural refinements. The guides cover advanced strategies for low-level programming, including the use of assembly for SIMD instructions and unsafe pointers for direct memory manipulation. It also details concurrency optimization techniques such as lock sharding and cache-line padding to reduce contention and improve hardware utilization. The material encompasses broad capabilit
Implements cache-line padding to prevent false sharing and reduce CPU cache coherence traffic.
xxHash is a high-performance, non-cryptographic hash library designed for rapid checksum generation and data integrity verification. It functions as an incremental hashing engine, allowing for the processing of large or streaming data inputs by maintaining a persistent internal state across sequential chunks. The library is engineered as a computational framework that maximizes throughput by utilizing wide CPU registers and branchless instruction pipelining. It achieves high-speed performance by aligning data access with CPU cache lines and employing multi-stage mixing functions that ensure c
Optimizes memory throughput by structuring data access patterns to fit within the CPU cache lines for faster retrieval.
This project is a specialized toolset for profiling kernel latency, analyzing tracepoint frequency, and monitoring system-wide performance data. It functions as a kernel performance profiler, tracepoint analyzer, and a collection of utilities for the Linux ftrace and perf_events subsystems. The toolkit provides high-level abstractions via shell-scripted wrappers to manage complex kernel tracing interfaces. It distinguishes itself through the use of bucket-based event histograms to visualize the distribution of kernel events and the ability to identify functions exceeding specific latency thre
Profiles memory access patterns and page cache statistics to detect performance bottlenecks.
Cutlass is a collection of C++ templates and Python interfaces for implementing high-performance linear algebra operations on NVIDIA GPUs. It provides a kernel composition framework for designing custom GPU kernels and a mixed-precision tensor library capable of executing operations across diverse data formats, ranging from 64-bit floating point to 4-bit integers. The project features a toolkit for operator fusion that integrates activation functions and bias calculations directly into matrix multiplication kernels to reduce memory passes. It also includes a Python-based domain-specific langu
Organizes data movement into structured blocks to maximize cache locality across the GPU memory hierarchy.
DeepEP is a distributed model accelerator and expert-parallel communication library designed to optimize the training and inference of large-scale neural networks. It provides specialized GPU communication kernels and a remote GPU memory interface to facilitate high-throughput data exchange between hardware nodes. The system utilizes dynamic kernel generation to compile optimized GPU kernels during execution, removing the need for separate installation compilation steps. It implements virtual-lane traffic isolation to prevent interference between different data streams and employs routing met
Utilizes low-level memory primitives to coordinate distributed parallelism and optimize hardware resource usage.
LeetCUDA is a collection of high-performance GPU kernel libraries focusing on memory optimization, activation functions, and attention mechanisms. It serves as a reference library for CUDA kernel implementations, ranging from basic element-wise operations to complex neural network components, and provides Python bindings to integrate these kernels into deep learning workflows. The project is distinguished by its focus on low-level hardware optimizations. This includes the use of tensor cores for half-precision matrix multiplication, asynchronous data pipelining with double buffering, and shar
Implements fine-grained tiling to manage memory usage and maintain constant complexity at the hardware level.
XiangShan is a high-performance RISC-V processor core and a hardware description language framework. It provides a construction-based system for designing, simulating, and verifying complex processor micro-architectures and peripheral devices. The project includes a high-performance CPU simulator used for architectural exploration and functional verification of processor execution. The project implements a superscalar out-of-order CPU architecture that uses renaming and reorder buffers to execute instructions in parallel. It generates synthesizable Verilog files from hardware descriptions to
Enhances memory access speed through the implementation of multi-port banked data arrays.
TIC-80 is a fantasy console platform and multi-language game engine that provides a virtual retro game development environment. It operates via a bytecode virtual machine that executes game logic within fixed memory and resolution constraints. The project distinguishes itself by offering integrated asset editors for pixel art, tile maps, and a pattern-based chiptune audio workstation all within a single environment. It supports multi-language scripting, allowing developers to write logic in Lua, JavaScript, or Ruby, and provides a standalone game exporter to package projects into native execu
Provides access to memory-mapped system registers for low-level hardware interaction within the virtual console.
Ce projet est un générateur d'ID unique distribué conçu pour produire des identifiants 64 bits globalement uniques et triables à travers plusieurs nœuds. Il implémente un algorithme compatible Snowflake qui empêche les collisions en combinant des horodatages, des identifiants de travailleur et des numéros de séquence en un seul entier. Le système inclut un orchestrateur d'ID de travailleur pour allouer et maintenir des identités de machine uniques pendant le démarrage et la migration de l'instance en utilisant des stratégies basées sur la base de données. Pour augmenter le débit des requêtes et réduire la latence, il utilise une couche de mise en cache à tampon circulaire qui pré-génère des identifiants et emploie un mécanisme de remplissage basé sur des seuils. Le logiciel fournit des capacités pour gérer les clés de base de données distribuées, coordonner les nœuds système et configurer la distribution des bits pour équilibrer les besoins de concurrence par rapport à la durée de vie du système. Il inclut également des utilitaires pour analyser les identifiants générés en leurs composants originaux.
Employs cache-line padding between buffer elements to eliminate false sharing and increase hardware throughput.
Flashlight est une bibliothèque de machine learning et de tenseurs autonome en C++ utilisée pour construire et entraîner des réseaux de neurones. Elle fonctionne comme un framework complet de réseaux de neurones et un moteur de différenciation automatique, fournissant les outils pour construire des graphes de calcul et calculer les gradients via la rétropropagation. Le projet sert de framework d'entraînement distribué, utilisant des opérations all-reduce pour synchroniser les gradients et les paramètres sur plusieurs nœuds de calcul et appareils. Il se distingue par une intégration profonde de la manipulation de tenseurs haute performance, l'interopérabilité native de la mémoire des appareils et un système pour synchroniser les poids entre les workers distribués afin d'accélérer l'entraînement de modèles à grande échelle. Le framework couvre un large éventail de capacités de deep learning, incluant la composition modulaire de couches pour concevoir des architectures complexes comme des blocs résiduels et des cellules récurrentes. Il fournit des utilitaires étendus de gestion de données pour l'ingestion et le préchargement, ainsi que des systèmes de sérialisation pour persister les états de modèle. De plus, il inclut une suite d'outils de surveillance et d'observabilité pour suivre les métriques d'entraînement et mesurer les erreurs de séquence. La bibliothèque est implémentée en C++.
Reduces memory allocations and improves performance by fusing multiple function calls into a single kernel call.
Il s'agit d'une implémentation cryptographique de la fonction Argon2, gourmande en mémoire, servant de bibliothèque de hachage de mots de passe et de fonction de dérivation de clé. Elle transforme les mots de passe et les sels en hashs sécurisés et génère des clés cryptographiques conçues pour résister aux attaques de craquage matériel à haute vitesse. La bibliothèque utilise une conception gourmande en mémoire qui nécessite une RAM importante pour empêcher l'accélération via GPU ou ASIC. Elle intègre un accès mémoire indépendant des données pour bloquer les attaques par canal auxiliaire (side-channel) et prend en charge l'intégration de clés secrètes ou de « peppers » pour protéger contre les attaques par force brute sur des sels compromis. Les capacités supplémentaires incluent l'encodage de hash de mot de passe pour le stockage et le transport, la possibilité de lier des hashs à des données contextuelles spécifiques, et une gestion sécurisée de la mémoire qui efface les tampons sensibles immédiatement après utilisation.
Employs data-independent memory access patterns to block side-channel timing attacks.
TileLang is a Python-embedded domain-specific language compiler that JIT-compiles and autotunes GPU kernels. It uses a tile-based DSL, automatic software pipelining, and parallel autotuning to generate optimized GPU kernels at runtime. It supports tensor core operations with Pythonic syntax, automatic memory management, and thread mapping. The compiler searches over tile sizes, thread counts, and scheduling policies, compiling and benchmarking candidates in parallel to find the fastest kernel. It also caches compiled binaries and tuning results to disk for reuse across sessions. TileLang inc
Optimizes memory access patterns using layout annotations, swizzling, and pipelining for GPU kernels.