verilator/verilator
Verilator
Verilator is a hardware simulation engine and toolchain that translates Verilog and SystemVerilog hardware description languages into optimized C++ or SystemC models. It functions as a compiler and transpiler, converting hardware designs into executable binaries to achieve high-speed simulation and integration into software environments.
The project distinguishes itself by focusing on simulation acceleration through the generation of optimized C++ classes and cycle-accurate models. It provides a SystemVerilog linter for static analysis of hardware designs and a hardware coverage analyzer to track functional and code coverage during the verification process.
The system covers a broad range of capabilities including hardware-software co-simulation via Direct Programming Interfaces and the serialization of signal activity into waveform trace files. It supports multi-threaded model execution, hierarchical verilation for large designs, and performance profiling to identify execution bottlenecks.
The toolchain allows for custom build configuration, including cross-compilation and containerized execution, and provides mechanisms for custom code injection into generated models.
Features
- Simulation Acceleration - Converts Verilog and SystemVerilog designs into optimized C++ or SystemC models to achieve high-speed simulation.
- Source-to-C Transpilers - Translates hardware description languages into optimized C++ or SystemC models for high-speed simulation.
- Hardware Simulation - Provides a simulation environment that executes compiled hardware models as high-performance C++ binaries.
- HDL Design Linting - Analyzes hardware description code for quality issues and common design errors to prevent bugs before simulation.
- Code Linters - Provides a static analysis tool that scans SystemVerilog code for quality issues and common design errors.
- Static Code Linting - Analyzes hardware source code before compilation to detect structural errors and non-synthesizable constructs.
- Direct Programming Interfaces - Implements the DPI standard for bidirectional function calls and data exchange between C++ and hardware logic.
- Hardware Interfacing - Connects hardware models to software environments using APIs, DPI, or VPI.
- Logic Waveform Analysis - Generates and exports VCD or FST trace files to visualize signal activity and timing behavior during simulation.
- Simulation Waveform Exports - Generates trace files and Gantt report waveforms to visualize signal activity and timing behavior.
- Parallel Workload Distribution - Distributes workloads across multiple CPU threads to increase throughput and speed up trace construction.
- Cycle-Accurate Emulators - Creates a software representation of hardware that simulates logic transitions at every clock tick.
- HDL Compilers - Translates Verilog and SystemVerilog code into optimized C++ or SystemC models for high-speed simulation.
- Bi-Directional Language Bridging - Implements a standardized bridge for bidirectional function calls and data exchange between C++ and hardware logic.
- Hardware Timing Modeling - Provides the ability to execute delay statements and event controls to model accurate hardware temporal behavior.
- Hardware-Software Domain Bridges - Integrates hardware models with software environments using C++ APIs and Direct Programming Interfaces for system testing.
- Interface Coverage Analysis - Allows excluding specific blocks of hardware description code from coverage metrics to focus on relevant logic.
- Performance and Resource Profilers - Measures execution time and resource usage to find and resolve efficiency bottlenecks in simulations.
- Hardware Diagnostics - Produces SARIF diagnostics and clock domain crossing checks to verify design quality and correctness.
- Constrained Random Verification - Generates constrained random test vectors using a solver to ensure comprehensive coverage of hardware edge cases.
- Hardware Signal Forcing - Creates public control signals that allow C++ code to force or release specific hardware signals during simulation.
- Hardware Signal Reading - Allows reading specific hardware signal values directly from C++ by declaring signals as public.
- Hardware Waveform Serialization - Records signal activity into VCD or FST formats by logging state changes during simulation runtime.
- Compiler-Based Instrumentation - Inserts probe points into the generated C++ model to record which logic paths are exercised during execution.
- Hierarchical Compilation - Splits massive designs into smaller models to reduce memory consumption and shorten compilation times.
- CPU Core Partitioning - Manages memory access strategies for thread pools to prioritize physical core usage and improve runtime speed.
- Multi-threaded Execution - Distributes the evaluation of independent hardware modules across multiple CPU cores to increase simulation throughput.
- Simulation Binary Generation - Produces standalone binary or library files that can be wrapped in custom code to execute design simulations.
- Execution Flow Visualizations - Records timing and task flow to generate Gantt charts and parallelism statistics for execution paths.
- Code Coverage Analysis - Tracks functional and code coverage to determine which parts of a hardware design were exercised during testing.
- State Transition Coverage - Identifies transparent state-register wrappers to extract and analyze finite state machine state and transition coverage.
- Functional Coverage Monitoring - Monitors covergroups and transition bins to measure the verification progress of a hardware design.
- Uninitialized Logic Detection - Uses random variable initialization and assignment strategies to uncover reset failures and uninitialized logic.
- Performance Profiling - Maps performance data back to original line numbers to identify and fix execution bottlenecks in source code.
- Hardware Core Verifications - Implements a verification workflow that collects code and functional coverage data to ensure design exercise.
