2 Repos
Awesome GitHub RepositoriesConstrained Random Verification
Techniques for generating random test vectors subject to specific constraints to exercise hardware edge cases.
Distinct from Random Value Generators: This is a domain-specific hardware verification technique using solvers, distinct from generic software random value generators.
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Awesome Constrained Random Verification GitHub Repositories
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- verilator/verilator
verilator/verilator
3,365Auf GitHub ansehenVerilator is a hardware simulation engine and toolchain that translates Verilog and SystemVerilog hardware description languages into optimized C++ or SystemC models. It functions as a compiler and transpiler, converting hardware designs into executable binaries to achieve high-speed simulation and integration into software environments. The project distinguishes itself by focusing on simulation acceleration through the generation of optimized C++ classes and cycle-accurate models. It provides a SystemVerilog linter for static analysis of hardware designs and a hardware coverage analyzer to t
Generates constrained random test vectors using a solver to ensure comprehensive coverage of hardware edge cases.
SystemVerilogcompilerscpprtl - ghdl/ghdl
ghdl/ghdl
2,759Auf GitHub ansehenGHDL is a compiler and simulator for VHDL hardware descriptions. It functions as a multi-pass analysis elaborator that resolves design hierarchies and dependencies to prepare hardware descriptions for simulation or synthesis. The project transforms VHDL source code into executable binaries for high-speed digital design verification and serves as a synthesis tool that converts descriptions into structural netlists compatible with vendor or open-source flows. It also implements the Language Server Protocol to provide static analysis, autocomplete, and code navigation for VHDL files. The toolse
Provides integration with external libraries to perform constrained random verification on hardware designs.
VHDLcompilergccghdl
