google/highway
Highway
Highway is a portable C++ library and hardware abstraction layer designed for writing single instruction multiple data (SIMD) code. It provides a unified interface that maps data-parallel logic to various CPU instruction sets, enabling the development of high-performance software that runs across different processor architectures without requiring architecture-specific assembly.
The project features a dynamic instruction dispatcher that selects the most efficient CPU instruction set at runtime based on detected hardware. It also supports static target specialization and extensible mechanisms for adding new hardware targets or custom SIMD operations.
The library covers a broad range of vector operations, including element-wise arithmetic, lane reduction, shuffling, and masked conditional execution. It includes a vectorized math library, a memory manager for aligned allocation and masked load-store operations, and primitives for hardware-accelerated cryptography.
Tooling is provided for the automated compilation and validation of hardware-accelerated instructions across multiple processor architectures.
Features
- Hardware Dispatchers - Features a dynamic dispatcher that detects CPU capabilities at startup to select the most efficient instruction set.
- Hardware Abstraction Layers - Acts as a hardware abstraction layer that maps processor-specific intrinsics into a unified C++ API.
- SIMD-Based Data Parallelism - Provides a portable interface to write data-parallel code that maps to hardware-accelerated SIMD instructions.
- Cross-Architecture Performance Strategies - Enables high-performance software execution across multiple processor types without requiring architecture-specific assembly.
- Instruction Set Targeting - Selects the best available CPU instruction set during program execution to maximize performance on heterogeneous hardware.
- Runtime Instruction Dispatchers - Ships a dynamic instruction dispatcher that selects the most efficient CPU instruction set based on detected hardware.
- SIMD Abstraction Layers - Provides a portable C++ template interface that maps to architecture-specific SIMD intrinsics at compile time.
- SIMD Libraries - Provides a portable C++ library for writing SIMD code that maps to various CPU instruction sets.
- Loop Vectorization - Provides a portable interface to implement loop vectorization using strip-mining strategies across various CPU architectures.
- Vector Masking and Reduction - Provides hardware-specific sum and max instructions to aggregate vector elements into scalar values.
- Conditional Execution Masks - Uses binary masks to control vector lane operations and avoid branching in data-parallel code.
- Hardware Instruction Targeting - Executes specialized code paths by targeting specific hardware instructions based on the detected CPU target.
- Vector Instruction Targets - Optimizes binaries by resolving specific SIMD instruction set targets like SSE or AVX during compilation.
- Vector Instruction Mapping - Provides a portable interface that maps data-parallel logic to architecture-specific vector instruction intrinsics.
- Custom SIMD Operations - Allows adding new hardware-accelerated functions by writing target-specific implementations for all supported architectures.
- SIMD Memory Alignment - Ensures memory allocations start on specific byte boundaries to maximize CPU cache efficiency and prevent faults.
- SIMD Memory Managers - Includes a memory manager for aligned allocation and masked load-store operations to optimize vector processing.
- High-Performance Data Analysis - Accelerates mathematical operations, sorting, and hashing using optimized low-level vector algorithmic toolkits.
- Vectorized Memory Access - Moves data between memory and registers using aligned, unaligned, masked, or interleaved access patterns.
- Masked Memory Operations - Implements masked load and store operations to prevent out-of-bounds memory access during partial vector processing.
- Vector Lane Shuffling - Implements vector lane shuffling including reverses, slides, and broadcasts to rearrange elements within registers.
- Cryptographic Accelerators - Implements hardware-accelerated cryptographic primitives and carryless multiplication using SIMD vector instructions.
- Hardware Target Extensions - Integrates new processor architectures by defining target identifiers and connecting them to dispatch mechanisms.
- Vector Element Comparison - Evaluates equality and relational conditions between vectors to create binary masks for conditional processing.
- Vector Mask Manipulation - Provides tools to create and combine binary masks for conditional execution on specific vector lanes.
- Vectorized Math Functions - Offers a vectorized math library for fast trigonometric, hyperbolic, and complex arithmetic using CPU instructions.
- Parallel Math Libraries - Provides a collection of hardware-accelerated functions for performing element-wise and complex math on vectors.
- Vector Mathematics - Implements hardware-accelerated dot products and other mathematical functions across various CPU architectures.
- Vector Arithmetic Operations - Provides hardware-accelerated element-wise arithmetic and fused multiply-add operations across diverse CPU architectures.
- Vector Type Converters - Provides functions for changing element widths and casting between integer and floating-point representations in vector registers.
- Conditional Vector Operations - Implements masked conditional execution to control which vector lanes perform operations without branching.
- Hardware-Accelerated Primitive Substitutions - Implements secure hashing and encryption rounds using processor-specific hardware-accelerated primitives.
- Compile-Time Metaprogramming - Implements compile-time logic to resolve optimal data types and vector widths across different hardware targets.
- Parallel Programming Frameworks - Performance-portable SIMD intrinsics for various architectures.
