8 Repos
Executes multiple data operations in a single instruction cycle to maximize throughput for high-bandwidth multimedia processing tasks.
Distinct from SIMD-Accelerated Arithmetic: Distinct from SIMD-Accelerated Arithmetic: focuses on the broader application of SIMD for data parallelism in multimedia rather than just arithmetic operations.
Explore 8 awesome GitHub repositories matching data & databases · SIMD-Based Data Parallelism. Refine with filters or upvote what's useful.
AISystem is a comprehensive AI full-stack infrastructure project covering the entire pipeline from AI chip architecture to high-level training frameworks. It encompasses the development of AI compiler frameworks, inference engines, and distributed training orchestrators designed to coordinate workloads across a heterogeneous compute stack of CPUs, GPUs, and NPUs. The project focuses on the deep integration of software and hardware, employing software-hardware co-design to align tensor layouts with physical memory structures. It provides specialized capabilities for accelerating Transformer mo
Applies a single instruction across multiple data elements simultaneously to accelerate vector operations.
This project serves as an educational resource for learning and implementing low-level assembly language optimizations. It provides a structured guide for developers to master hardware-specific instructions and manual performance tuning, focusing on the translation of high-level code into efficient machine-level operations for resource-constrained environments. The materials emphasize techniques for maximizing computational throughput in multimedia processing. By covering instruction-level parallelism, register management, and data parallelism, the project enables the development of software
Executes multiple data operations in a single instruction cycle to maximize throughput for high-bandwidth multimedia processing tasks.
xxHash is a high-performance, non-cryptographic hash library designed for rapid checksum generation and data integrity verification. It functions as an incremental hashing engine, allowing for the processing of large or streaming data inputs by maintaining a persistent internal state across sequential chunks. The library is engineered as a computational framework that maximizes throughput by utilizing wide CPU registers and branchless instruction pipelining. It achieves high-speed performance by aligning data access with CPU cache lines and employing multi-stage mixing functions that ensure c
Processes data in parallel using wide CPU registers to maximize throughput during large memory block hashing operations.
BLAKE3 ist eine Hochleistungs-Implementierung des kryptografischen BLAKE3-Hash-Algorithmus zur Berechnung sicherer Daten-Digests und Fingerabdrücke. Es fungiert als paralleles kryptografisches Hash-Tool, das Workloads über mehrere Prozessor-Threads verteilt, um große Datensätze schnell zu verarbeiten. Das Projekt bietet spezialisierte Tools für Keyed-Hashing und die Generierung von Message Authentication Codes. Es enthält zudem Funktionen für die kryptografische Schlüsselableitung, die die Erstellung eindeutiger geheimer Sub-Keys aus einem Master-Key und Kontext-Strings ermöglichen. Die Implementierung unterstützt die Integritätsprüfung von Daten durch parallele Hash-Berechnung und verifiziertes Daten-Streaming. Diese Funktionen werden als sprachübergreifende Bibliothek für Rust- und C-Umgebungen bereitgestellt und enthalten eine Kommandozeilenschnittstelle zur Berechnung von Digests für Dateien oder Standard-Eingaben.
Maximizes CPU throughput by processing multiple data blocks simultaneously using SIMD lanes.
Highway is a portable C++ library and hardware abstraction layer designed for writing single instruction multiple data (SIMD) code. It provides a unified interface that maps data-parallel logic to various CPU instruction sets, enabling the development of high-performance software that runs across different processor architectures without requiring architecture-specific assembly. The project features a dynamic instruction dispatcher that selects the most efficient CPU instruction set at runtime based on detected hardware. It also supports static target specialization and extensible mechanisms
Provides a portable interface to write data-parallel code that maps to hardware-accelerated SIMD instructions.
c3c is the compiler for the C3 programming language, transforming source code into executable binaries, static libraries, or dynamic libraries using an LLVM backend. It implements a system based on result-based error handling, scoped memory pooling, and a semantic macro system. The compiler provides first-class support for hardware-backed SIMD vectors that map directly to processor instructions and enables runtime polymorphism through interface-based dynamic dispatch. The project covers a broad set of low-level capabilities, including manual and pooled memory management, inline assembly inte
Executes parallel arithmetic and logical operations on hardware-backed vectors to maximize computational throughput.
Rack is a virtual Eurorack modular synthesizer emulator and a modular synthesis SDK. It provides a digital environment for creating and routing electronic music signals using virtual modules, oscillators, and filters, simulating the behavior of analog hardware through voltage-based signal routing. The system functions as a MIDI and CV converter, translating signals between software and external hardware, and can operate as a VST or industry-standard instrument plugin within digital audio workstations. It also acts as a VST plugin host, embedding external virtual instruments and effects to exp
Utilizes SIMD vector instructions to process multiple audio channels in parallel for CPU efficiency.
perf-ninja is a collection of educational resources and curricula focused on CPU architecture, memory hierarchies, SIMD programming, and low-level performance engineering. It provides instructional material and practical labs for identifying and fixing CPU bottlenecks, such as cache misses and branch mispredictions. The project differentiates itself through specialized training in hardware-level optimizations, including the use of compiler intrinsics for SIMD vectorization and the implementation of branchless predicate execution to eliminate pipeline stalls. It also covers advanced binary-lev
Provides guidance on replacing scalar operations with hardware-specific vector instructions to process multiple data elements simultaneously.