Awesome GitHub RepositoriesHardware Capability Modeling

AISystem is a comprehensive AI full-stack infrastructure project covering the entire pipeline from AI chip architecture to high-level training frameworks. It encompasses the development of AI compiler frameworks, inference engines, and distributed training orchestrators designed to coordinate workloads across a heterogeneous compute stack of CPUs, GPUs, and NPUs. The project focuses on the deep integration of software and hardware, employing software-hardware co-design to align tensor layouts with physical memory structures. It provides specialized capabilities for accelerating Transformer mo

This project is an open-source software development kit and framework for implementing the Matter smart home standard. It provides a universal IPv6-based application layer and a cluster-based data model to ensure interoperability between diverse smart home devices and controllers. The system is distinguished by its multi-transport network abstraction, which maps Bluetooth LE, Thread, and Wi-Fi implementations to a common layer. It includes specialized tooling for secure device commissioning via QR codes and NFC, as well as a comprehensive over-the-air firmware update system for distributing s

Qiskit is a quantum computing software development kit used for designing, simulating, and executing quantum circuits on physical hardware and simulators. It functions as a quantum algorithm framework, a circuit simulator, and a vendor-agnostic hardware interface for dispatching workloads across diverse providers. The project features a quantum circuit transpiler that optimizes abstract designs to match the specific basis gates and qubit connectivity of target hardware. It employs a pass-based transpilation pipeline and symbolic instruction translation to convert high-level circuits into hard

Digital es un simulador de circuitos de lógica digital y herramienta de verificación de diseño de hardware. Proporciona un entorno visual para diseñar, probar y verificar circuitos electrónicos utilizando simulación basada en eventos y síntesis lógica automatizada. La plataforma funciona como una herramienta de síntesis lógica que aplica álgebra booleana para minimizar configuraciones de puertas y convertir tablas de verdad en hardware eficiente. También sirve como herramienta de exportación HDL, traduciendo grafos de circuitos visuales a código VHDL o Verilog, y como herramienta de despliegue CPLD que genera archivos JEDEC para programar chips de lógica programable. El software cubre una amplia gama de capacidades, incluyendo el diseño de máquinas de estados finitos, la organización jerárquica y parametrizada de circuitos, y la visualización del estado de las señales. Incluye utilidades para la verificación lógica automatizada, el seguimiento de la propagación de señales y una interfaz remota basada en TCP para la gestión del simulador y la depuración de sistemas embebidos.

CloverBootloader is a UEFI-compliant boot loader designed to initialize hardware and launch multiple operating systems across various platforms. Its primary purpose is to enable the booting of operating systems on unsupported hardware through system identity spoofing and hardware emulation. The project specializes in hardware compatibility patching by modifying ACPI tables, faking hardware IDs, and patching binary kernels or extensions in memory during the boot process. It provides capabilities to inject kernel extensions and spoof system parameters, such as product names and serial numbers,

Cirq es un framework de computación cuántica en Python utilizado para diseñar, simular y ejecutar circuitos cuánticos en hardware cuántico de escala intermedia ruidosa (NISQ). Sirve como simulador de circuitos cuánticos y modelador de ruido, así como una herramienta para la implementación de algoritmos cuánticos. El framework proporciona una interfaz especializada para hardware NISQ, permitiendo a los usuarios mapear circuitos cuánticos lógicos a topologías de dispositivos físicos mientras validan la conectividad del hardware y las restricciones de las puertas. Se distingue por su modelado de ruido integrado, aplicando canales de despolarización y amortiguación para imitar la decoherencia y los errores encontrados en procesadores cuánticos reales. El proyecto cubre una amplia gama de capacidades, incluyendo el diseño de circuitos cuánticos, la integración de hardware y la simulación de estados. Incluye herramientas para la descomposición de puertas, el mapeo de topología de hardware y la ejecución de procedimientos cuánticos fundamentales como transformadas de Fourier y búsqueda de datos no estructurados. Además, proporciona utilidades analíticas para el cálculo del estado fundamental molecular y la evaluación comparativa de la fidelidad del hardware.

Chisel is a hardware construction language and description tool used to define digital circuits. It functions as a generator that converts high-level hardware descriptions into synthesizable Verilog code for use in ASIC and FPGA design. The project enables the creation of parameterizable hardware templates and reusable digital components. It leverages functional and object-oriented programming patterns to transform complex circuit representations into finalized hardware descriptions. The toolset covers the register-transfer level design workflow, allowing users to model digital circuits usin

MobileModels es una base de datos de hardware de dispositivos móviles y un registro de identificación de modelos. Sirve como una colección estructurada que mapea nombres comerciales de consumo a números de modelo del fabricante y nombres en clave de hardware internos. El proyecto funciona como un directorio de variantes de hardware, distinguiendo entre diferentes versiones regionales y de operador del mismo dispositivo a través de varias marcas. Incluye un rastreador de bootloader y kernel para monitorear la disponibilidad de lanzamientos oficiales de código fuente del kernel y el estado de desbloqueo del bootloader. El registro cubre la catalogación de hardware móvil mediante el mapeo de identificadores de dispositivos y el análisis de las convenciones de nomenclatura del fabricante para decodificar números de modelo. Proporciona una referencia para vincular especificaciones de hardware y SKU regionales a sus correspondientes nombres en clave de desarrollo.

picorv32 is a size-optimized RISC-V CPU core and synthesizable processor IP designed for integration into FPGA and ASIC hardware designs. It serves as an open-source CPU architecture and embedded system-on-chip component that implements a standard RISC-V instruction set. The design features a modular architecture that allows for the integration of external coprocessors to implement custom non-branching instructions. It includes a parameterized integer unit with configurable multiplication and division cores to balance performance against total logic gate count. The project covers a broad ran

Quantum is a quantum development framework that provides a hybrid quantum-classical workflow for coordinating execution between classical host languages and quantum processors. It includes a quantum hardware simulator for modeling state evolution and a library of quantum algorithms for tasks such as integer factorization, database search, and quantum arithmetic. The project offers specialized tools for quantum hardware characterization and error correction to manage noise and decoherence. It provides resource estimation modeling to calculate the qubit count and gate depth required to execute

Rocket-chip is a framework for the parametric design, synthesis, and verification of RISC-V based processors and system-on-chip hardware. It functions as a generator that converts high-level specifications into synthesizable Verilog files for FPGA or ASIC implementation. The project utilizes a Scala-based hardware description framework to produce customizable pipelined processor cores, memory hierarchies, and peripheral devices. It employs a parameter-driven model and a two-phase negotiation process to resolve hardware interface specifications between modules during the elaboration phase. Th

This project is a smart home automation framework and a library of device drivers and handlers designed to integrate hardware into the SmartThings ecosystem. It functions as an IoT device handler repository that translates proprietary hardware signals into standard commands for a central hub. The system emphasizes a local hub rules engine to execute automation logic and device routines directly on hardware, reducing reliance on cloud processing. It provides a collection of custom drivers specifically for managing Zigbee, Z-Wave, and LAN devices. The framework covers the development of custom

This project is an open-source computer-aided design toolchain designed for the synthesis, placement, and routing of hardware designs onto programmable logic architectures. It serves as a comprehensive framework for research and development, enabling the transformation of hardware description language designs into optimized netlists and physical implementation files. By providing a modular pipeline, the system facilitates the entire flow from initial logic synthesis to the generation of configuration data for programmable hardware devices. The toolchain distinguishes itself through its focus