plaidml/plaidmlArchived
Plaidml
PlaidML 是一个深度学习编译器框架和跨平台运行时，旨在在各种硬件目标上执行机器学习模型。它作为一个硬件无关的张量引擎，将张量模型翻译为可执行代码，从而允许深度学习网络在不同计算设备上运行，而无需特定的驱动程序依赖。
该系统通过使用 JSON 规范定义设备硬件，实现了在自定义或受限硬件上执行模型。它采用领域特定语言来描述张量计算，并提供中间层将各种机器学习框架与其硬件目标编译器集成。
该引擎支持一系列张量操作，包括带索引约束的张量收缩、带可配置步长和填充的多维卷积，以及使用广播的逐元素操作。它还包含一个测试套件，用于基准测试不同硬件组件和环境下的执行速度和效率。
Features
- Cross-Platform Model Execution - Runs machine learning models across different hardware targets and operating systems to verify correctness and measure performance.
- Cross-Platform Runtimes - Provides a software layer that enables consistent model execution across diverse hardware architectures using JSON specifications.
- Backend-Agnostic Deep Learning - Executes deep learning models across diverse hardware targets without requiring vendor-specific drivers or software.
- Framework-Agnostic Backends - Acts as a framework-agnostic backend that connects various machine learning frameworks to a universal hardware-targeting compiler.
- Model Compilers - Transforms high-level neural network definitions into optimized, hardware-specific executable code.
- Hardware Acceleration - Utilizes specialized hardware components and custom specifications to enhance computational throughput for machine learning tasks.
- Backend-Agnostic Engines - Decouples neural network operations from specific hardware backends to enable cross-platform execution without driver dependencies.
- JSON Device Specifications - Defines hardware specifications in JSON files to allow model execution on devices without native software support.
- Device Support Specifications - Defines device specifications in JSON files to run models on hardware with limited or custom software support.
- AOT Deep Learning Compilers - Translates neural network graphs into standalone native code for efficient hardware-targeted inference.
- Tensor Operation Definitions - Provides a domain-specific language to describe tensor computations that are subsequently converted into hardware-specific implementations.
- Hardware-Targeted Compilation - Translates high-level tensor networks into executable code optimized for the specific constraints of chosen hardware targets.
- Deep Learning Execution - Executes tensor networks and deep learning models across diverse hardware targets to verify correctness and performance.
- Configurable Convolutions - Constructs multi-dimensional convolutions using configurable strides, dilation rates, padding, and grouping.
- Neural Network Operations - Defines mathematical operations and transformations used within neural network layers.
- ML Framework Integrations - Connects tensor compilers to various machine learning frameworks to enable execution across diverse hardware targets.
- Tensor Broadcasting - Implements mechanisms for performing element-wise operations on tensors with different shapes through automatic broadcasting.
- Index Range Constraints - Restricts the range of index variables during tensor contractions to implement pooling or cumulative sums.
- Tensor Contractions - Aggregates values across tensor indices using sum, max, min, or product operations to reduce dimensionality.
- Index-Constrained Contractions - Reduces tensor dimensionality by aggregating values across indices while applying specific range constraints for pooling and sums.
- Tensor Operations - Performs mathematical functions and binary operators on tensor elements using broadcasting for mismatched shapes.
- Tensor Network Executors - Implements a tensor engine for performing contractions and elementwise operations on diverse hardware.
- Hardware Performance Benchmarking - Compares execution speed and efficiency across different hardware components and environments using a dedicated testing suite.
