Bitwise is a computer architecture education kit and a comprehensive set of guides for building a custom CPU, operating system, and compiler from scratch. It serves as a CPU design tutorial and a practical framework for implementing a unique instruction set architecture.
pervognsen/bitwise 的主要功能包括:Computer Systems Education, Step-by-Step Tutorials, Full-Stack Systems Engineering, Task Schedulers, Computer Architecture Curricula, Control Logic Design, Custom CPU Architecture Design, FPGA Hardware Design。
pervognsen/bitwise 的开源替代品包括: gurugio/lowlevelprogramming-university — This project is a comprehensive educational framework designed to guide learners through the complexities of systems… geohot/fromthetransistor — This project consists of technical instructional guides and a structured computer science curriculum designed to teach… serenityos/serenity — SerenityOS is a complete, self-hosted desktop operating system built from the kernel up. It features a monolithic… ghdl/ghdl — GHDL is a compiler and simulator for VHDL hardware descriptions. It functions as a multi-pass analysis elaborator that… yosyshq/picorv32 — picorv32 is a size-optimized RISC-V CPU core and synthesizable processor IP designed for integration into FPGA and… amhndu/simplenes — SimpleNES is a C++ application that simulates original Nintendo Entertainment System hardware to run legacy games on…
This project is a comprehensive educational framework designed to guide learners through the complexities of systems engineering and low-level software development. It provides structured learning paths that integrate hardware simulation, source code analysis, and project-based exercises to help developers master the foundational concepts of computer architecture, operating systems, and firmware design. The curriculum distinguishes itself by emphasizing direct interaction with system internals, requiring learners to examine and modify existing open-source kernel and driver implementations. By
This project consists of technical instructional guides and a structured computer science curriculum designed to teach the construction of a full computing stack from transistors up to a web browser. It provides a 12-week educational course that covers the fundamental domains of computer architecture and digital logic design. The curriculum is distinguished by its first-principles approach, guiding the learner through the engineering of CPUs, FPGAs, and PCBs using digital logic and hardware description languages. It includes specific syllabi for building a hardware design, a TCP/IP network st
SerenityOS is a complete, self-hosted desktop operating system built from the kernel up. It features a monolithic kernel architecture that manages system services, hardware drivers, and networking within a single address space. The system provides a full computing environment, including a proprietary windowing system and a suite of native desktop applications, all while maintaining a POSIX-compliant interface for standard system programming. The project is distinguished by its integrated development workflow, which relies on a cross-compilation build pipeline to generate system images from ho
GHDL is a compiler and simulator for VHDL hardware descriptions. It functions as a multi-pass analysis elaborator that resolves design hierarchies and dependencies to prepare hardware descriptions for simulation or synthesis. The project transforms VHDL source code into executable binaries for high-speed digital design verification and serves as a synthesis tool that converts descriptions into structural netlists compatible with vendor or open-source flows. It also implements the Language Server Protocol to provide static analysis, autocomplete, and code navigation for VHDL files. The toolse