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Awesome GitHub RepositoriesHardware Data Prefetching
Mechanisms to load data into CPU caches before explicit requests using stride or temporal patterns.
Distinct from Data Prefetching: Candidates focus on web data, DNS, or ML training batches, not CPU micro-architectural prefetching.
Explore 1 awesome GitHub repository matching operating systems & systems programming · Hardware Data Prefetching. Refine with filters or upvote what's useful.
Awesome Hardware Data Prefetching GitHub Repositories
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- openxiangshan/xiangshan
OpenXiangShan/XiangShan
7,081在 GitHub 上查看XiangShan is a high-performance RISC-V processor core and a hardware description language framework. It provides a construction-based system for designing, simulating, and verifying complex processor micro-architectures and peripheral devices. The project includes a high-performance CPU simulator used for architectural exploration and functional verification of processor execution. The project implements a superscalar out-of-order CPU architecture that uses renaming and reorder buffers to execute instructions in parallel. It generates synthesizable Verilog files from hardware descriptions to
Reduces data access penalties via spatial memory streaming and stride or temporal prefetching patterns.
Scalachiselmicroarchitecturerisc-v
