chipsalliance/rocket-chip
Rocket Chip
Rocket-chip is a framework for the parametric design, synthesis, and verification of RISC-V based processors and system-on-chip hardware. It functions as a generator that converts high-level specifications into synthesizable Verilog files for FPGA or ASIC implementation.
The project utilizes a Scala-based hardware description framework to produce customizable pipelined processor cores, memory hierarchies, and peripheral devices. It employs a parameter-driven model and a two-phase negotiation process to resolve hardware interface specifications between modules during the elaboration phase.
The capability surface includes the generation of memory-mapped peripherals, hardware bus implementations, and a verification suite featuring randomized testbenches for stress testing memory hierarchies. It also provides toolchain provisioning to ensure reproducible development and simulation environments through hash-based dependency locking.
Features
- Hardware Description Frameworks - Provides a Scala-based hardware description framework for generating synthesizable hardware micro-architectures.
- RISC-V Processor Cores - Creates custom RISC-V processor cores and system-on-chip architectures from high-level specifications.
- Automated Hardware Generation - Implements a generative process that transforms high-level configurations into synthesizable hardware descriptions.
- Verilog Generators - Translates high-level Scala specifications into synthesizable Verilog hardware descriptions.
- Instruction Pipeline Architectures - Implements a classic instruction pipeline with dedicated stages for fetch, decode, execute, and memory access.
- Hardware Parameterization Libraries - Provides a parameterization library to define hardware specifications and customize generated descriptions.
- Parameterized Circuit Design - Defines and negotiates hardware specifications across modules to automate custom chip design generation.
- Parametric Hardware Generators - Uses a library of configurable parameters to automatically synthesize processor cores and system-on-chip layouts.
- Parametric Processor Generators - Provides a framework for the parametric design and synthesis of pipelined processor cores.
- Pipelined Core Generators - Generates pipelined cores with instruction and data caches extensible with floating-point units and accelerators.
- System-on-Chip Integration - Produces synthesizable hardware descriptions for processors, memory hierarchies, and peripherals.
- Hardware Core Verifications - Includes a verification suite using randomized testbenches to ensure architectural compliance of processor cores.
- Peripheral Mappings - Connects debug modules and JTAG interfaces to the processor via standardized memory-mapped register buses.
- Hardware Design Toolchains - Sets up reproducible development environments with specific compiler and toolchain versions for synthesis.
- Hardware Synthesis Compilation - Converts high-level hardware descriptions into synthesizable Verilog using specified build tools.
- Reproducible Build Environments - Provides specifications for exact versions and source hashes of tools to ensure consistent build environments.
- Development Environment Reproducibility - Creates a reproducible shell containing all necessary compilers and toolchains for hardware simulation.
- Hardware Bus Generators - Generates hardware bus implementations for standard communication protocols using dynamic parameter negotiation.
- Hardware Description Exporters - Provides utilities to export internal circuit representations into standardized hardware description formats.
- Hardware Parameter Negotiation - Resolves hardware interface specifications between modules by exchanging parameters during a separate elaboration phase.
- Peripheral Integration - Integrates JTAG interfaces, register slaves, and debug devices into the overall SoC hardware design.
- Peripheral Hardware Generators - Generates hardware implementations for debug modules, JTAG interfaces, and memory-mapped register slave devices.
- Two-Phase Compilation - Facilitates the exchange and agreement of hardware parameters between components during a two-phase elaboration process.
- Toolchain Version Locking - Ensures reproducible build environments by locking compilers and toolchains to specific source versions and hashes.
- Hardware Test Bench Generation - Automates the creation of simulation environments and testbenches to verify hardware design states.
- Randomized Hardware Testbenches - Verifies memory hierarchies by generating synthesizable testers that inject randomized memory access patterns.
