2 repository-uri
Awesome GitHub RepositoriesBandwidth Maximization
Techniques using high-bandwidth memory and on-chip buffers to reduce data movement latency.
Distinct from Memory Access Pattern Optimizers: Distinct from Memory Access Pattern Optimizers: focuses on the hardware resource utilization (HBM, on-chip buffers) to reduce latency rather than just the software access pattern
Explore 2 awesome GitHub repositories matching software engineering & architecture · Bandwidth Maximization. Refine with filters or upvote what's useful.
Awesome Bandwidth Maximization GitHub Repositories
Găsește cele mai bune repo-uri cu AI.Vom căuta cele mai potrivite repository-uri folosind AI.
- infrasys-ai/aisystem
Infrasys-AI/AISystem
17,017Vezi pe GitHubAISystem is a comprehensive AI full-stack infrastructure project covering the entire pipeline from AI chip architecture to high-level training frameworks. It encompasses the development of AI compiler frameworks, inference engines, and distributed training orchestrators designed to coordinate workloads across a heterogeneous compute stack of CPUs, GPUs, and NPUs. The project focuses on the deep integration of software and hardware, employing software-hardware co-design to align tensor layouts with physical memory structures. It provides specialized capabilities for accelerating Transformer mo
Uses high-bandwidth memory and on-chip buffers to reduce movement latency and minimize external memory access for large parameters.
Jupyter Notebookaiaiinfraaisys - openxiangshan/xiangshan
OpenXiangShan/XiangShan
7,081Vezi pe GitHubXiangShan is a high-performance RISC-V processor core and a hardware description language framework. It provides a construction-based system for designing, simulating, and verifying complex processor micro-architectures and peripheral devices. The project includes a high-performance CPU simulator used for architectural exploration and functional verification of processor execution. The project implements a superscalar out-of-order CPU architecture that uses renaming and reorder buffers to execute instructions in parallel. It generates synthesizable Verilog files from hardware descriptions to
Enhances memory access speed through the implementation of multi-port banked data arrays.
Scalachiselmicroarchitecturerisc-v
