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13 repository-uri

Awesome GitHub RepositoriesCache-Aware Memory Access

Aligns data structures and access patterns to hardware cache lines to prevent performance degradation from frequent main memory fetches.

Distinct from Memory Access Profilers: Distinct from Memory Access Profilers: focuses on active data alignment and access pattern optimization rather than passive profiling.

Explore 13 awesome GitHub repositories matching software engineering & architecture · Cache-Aware Memory Access. Refine with filters or upvote what's useful.

Awesome Cache-Aware Memory Access GitHub Repositories

Găsește cele mai bune repo-uri cu AI.Vom căuta cele mai potrivite repository-uri folosind AI.
  • lemire/simdjsonAvatar lemire

    lemire/simdjson

    23,860Vezi pe GitHub↗

    simdjson is a high-performance JSON parser that utilizes SIMD instructions to process gigabytes of data per second. It functions as a SIMD JSON parser, a multithreaded NDJSON processing library, a UTF-8 validation engine, and a tool for JSON minification and string building. The project focuses on high-throughput data processing, enabling the ingestion of massive JSON volumes and the verification of UTF-8 encoding standards. It includes dedicated capabilities for constructing JSON strings with optimized memory usage and removing unnecessary whitespace from documents to reduce file size. The

    Allocates extra space at the end of buffers to allow wide SIMD loads without memory access violations.

    C++
    Vezi pe GitHub↗23,860
  • lmax-exchange/disruptorAvatar LMAX-Exchange

    LMAX-Exchange/disruptor

    18,375Vezi pe GitHub↗

    The Disruptor is a lock-free inter-thread messaging library and high-performance event bus. It implements a concurrent ring buffer designed for high-concurrency and low-latency message sequencing. The project utilizes a specific messaging architecture to eliminate lock contention, enabling high-throughput event routing and the exchange of continuous event streams between threads. It ensures strict first-in-first-out ordering and immediate data visibility across processing threads. The library provides capabilities for lock-free data streaming, sequential data ordering, and sequence-based eve

    Implements cache-line padding to eliminate false sharing and maximize CPU cache efficiency.

    Javaconcurrencydisruptorjava
    Vezi pe GitHub↗18,375
  • ffmpeg/asm-lessonsAvatar FFmpeg

    FFmpeg/asm-lessons

    12,067Vezi pe GitHub↗

    This project serves as an educational resource for learning and implementing low-level assembly language optimizations. It provides a structured guide for developers to master hardware-specific instructions and manual performance tuning, focusing on the translation of high-level code into efficient machine-level operations for resource-constrained environments. The materials emphasize techniques for maximizing computational throughput in multimedia processing. By covering instruction-level parallelism, register management, and data parallelism, the project enables the development of software

    Aligns data structures and access patterns to hardware cache lines to prevent performance degradation from frequent main memory fetches.

    Vezi pe GitHub↗12,067
  • dgryski/go-perfbookAvatar dgryski

    dgryski/go-perfbook

    10,902Vezi pe GitHub↗

    This project is a collection of educational resources and technical guides focused on Go performance optimization. It provides instruction on improving execution speed and reducing memory usage through code and architectural refinements. The guides cover advanced strategies for low-level programming, including the use of assembly for SIMD instructions and unsafe pointers for direct memory manipulation. It also details concurrency optimization techniques such as lock sharding and cache-line padding to reduce contention and improve hardware utilization. The material encompasses broad capabilit

    Implements cache-line padding to prevent false sharing and reduce CPU cache coherence traffic.

    optimizationperformanceperformance-analysis
    Vezi pe GitHub↗10,902
  • cyan4973/xxhashAvatar Cyan4973

    Cyan4973/xxHash

    10,885Vezi pe GitHub↗

    xxHash is a high-performance, non-cryptographic hash library designed for rapid checksum generation and data integrity verification. It functions as an incremental hashing engine, allowing for the processing of large or streaming data inputs by maintaining a persistent internal state across sequential chunks. The library is engineered as a computational framework that maximizes throughput by utilizing wide CPU registers and branchless instruction pipelining. It achieves high-speed performance by aligning data access with CPU cache lines and employing multi-stage mixing functions that ensure c

    Optimizes memory throughput by structuring data access patterns to fit within the CPU cache lines for faster retrieval.

    Ccdispersionhash
    Vezi pe GitHub↗10,885
  • deepseek-ai/deepepAvatar deepseek-ai

    deepseek-ai/DeepEP

    9,736Vezi pe GitHub↗

    DeepEP is a distributed model accelerator and expert-parallel communication library designed to optimize the training and inference of large-scale neural networks. It provides specialized GPU communication kernels and a remote GPU memory interface to facilitate high-throughput data exchange between hardware nodes. The system utilizes dynamic kernel generation to compile optimized GPU kernels during execution, removing the need for separate installation compilation steps. It implements virtual-lane traffic isolation to prevent interference between different data streams and employs routing met

    Utilizes low-level memory primitives to coordinate distributed parallelism and optimize hardware resource usage.

    Cuda
    Vezi pe GitHub↗9,736
  • baidu/uid-generatorAvatar baidu

    baidu/uid-generator

    5,572Vezi pe GitHub↗

    Acest proiect este un generator de ID-uri unice distribuit, conceput pentru a produce identificatori unici globali și sortabili pe 64 de biți pe mai multe noduri. Implementează un algoritm compatibil cu Snowflake care previne coliziunile prin combinarea timestamp-urilor, identificatorilor de worker și numerelor de secvență într-un singur întreg. Sistemul include un orchestrator de ID-uri de worker pentru a aloca și menține identități unice de mașină în timpul pornirii și migrării instanței folosind strategii bazate pe baze de date. Pentru a crește throughput-ul cererilor și a reduce latența, utilizează un strat de caching de tip ring-buffer care pre-generează identificatori și folosește un mecanism de reumplere bazat pe praguri. Software-ul oferă capabilități pentru gestionarea cheilor de baze de date distribuite, coordonarea nodurilor de sistem și configurarea distribuției biților pentru a echilibra nevoile de concurență față de durata de viață a sistemului. Include, de asemenea, utilitare pentru parsarea identificatorilor generați înapoi în componentele lor originale.

    Employs cache-line padding between buffer elements to eliminate false sharing and increase hardware throughput.

    Java
    Vezi pe GitHub↗5,572
  • p-h-c/phc-winner-argon2Avatar P-H-C

    P-H-C/phc-winner-argon2

    5,309Vezi pe GitHub↗

    Aceasta este o implementare criptografică a funcției memory-hard Argon2, servind drept bibliotecă de hashing a parolelor și funcție de derivare a cheilor. Transformă parolele și salt-urile în hash-uri securizate și generează chei criptografice concepute pentru a rezista atacurilor de spargere hardware de mare viteză. Biblioteca utilizează un design memory-hard care necesită o cantitate semnificativă de RAM pentru a preveni accelerarea prin GPU-uri sau ASIC-uri. Încorporează accesul la memorie independent de date pentru a bloca atacurile de tip side-channel timing și suportă integrarea cheilor secrete sau a „piper-ilor” pentru a proteja împotriva atacurilor de tip brute-force asupra salt-urilor compromise. Capabilitățile suplimentare includ codificarea hash-urilor de parole pentru stocare și transport, capacitatea de a lega hash-urile de date de context specifice și gestionarea securizată a memoriei care șterge bufferele sensibile imediat după utilizare.

    Employs data-independent memory access patterns to block side-channel timing attacks.

    C
    Vezi pe GitHub↗5,309
  • parallel101/courseAvatar parallel101

    parallel101/course

    4,166Vezi pe GitHub↗

    This project is a technical curriculum and set of educational resources focused on parallel programming, high-performance computing, and systems programming. It provides a structured course covering the implementation of parallel algorithms and multithreading techniques for processing large datasets. The project includes a systems programming guide for modern language features, a framework for lock-free concurrency patterns, and a manual for optimizing CPU and GPU performance through assembly analysis and cache management. The material covers hardware performance tuning, the implementation o

    Provides techniques for aligning data structures and access patterns to maximize CPU cache hits.

    C++coursecppcpp17
    Vezi pe GitHub↗4,166
  • cch123/golang-notesAvatar cch123

    cch123/golang-notes

    4,032Vezi pe GitHub↗

    This project is a technical reference and a collection of internal analysis notes focused on the Go language runtime and compiler. It provides a detailed breakdown of the language internals, covering memory management, garbage collection, and the execution model of the scheduler. The material distinguishes itself by providing deep dives into low-level system details, including a reference for Go assembly instructions, register usage, and system call interfacing. It specifically analyzes the internal implementation of concurrency primitives, such as the goroutine scheduling mechanism, channel

    Details the use of padding bytes to prevent CPU cache coherence traffic caused by false sharing.

    HTMLcodegogolang
    Vezi pe GitHub↗4,032
  • jctools/jctoolsAvatar JCTools

    JCTools/JCTools

    3,851Vezi pe GitHub↗

    JCTools is a Java concurrency library providing a collection of lock-less and wait-free data structures. It serves as a toolkit for managing thread-safe data exchange, specifically designed to optimize high-throughput messaging and producer-consumer patterns in multi-threaded applications. The library distinguishes itself by implementing specialized queue structures that minimize contention and maximize throughput. By utilizing techniques such as cache-line padding, memory-barrier-based synchronization, and relaxed-consistency memory ordering, it avoids the performance bottlenecks often assoc

    Aligns data structures to CPU cache lines to prevent false sharing and performance degradation in concurrent environments.

    Javaawesomebenchmarksconcurrency
    Vezi pe GitHub↗3,851
  • dendibakh/perf-ninjaAvatar dendibakh

    dendibakh/perf-ninja

    3,754Vezi pe GitHub↗

    perf-ninja is a collection of educational resources and curricula focused on CPU architecture, memory hierarchies, SIMD programming, and low-level performance engineering. It provides instructional material and practical labs for identifying and fixing CPU bottlenecks, such as cache misses and branch mispredictions. The project differentiates itself through specialized training in hardware-level optimizations, including the use of compiler intrinsics for SIMD vectorization and the implementation of branchless predicate execution to eliminate pipeline stalls. It also covers advanced binary-lev

    Teaches how to align data structures to cache line boundaries and implement loop tiling to minimize cache misses.

    C++
    Vezi pe GitHub↗3,754
  • open-quantum-safe/liboqsAvatar open-quantum-safe

    open-quantum-safe/liboqs

    2,979Vezi pe GitHub↗

    Liboqs este o bibliotecă C care oferă o interfață unificată pentru algoritmi criptografici rezistenți la computerele cuantice, inclusiv mecanisme de încapsulare a cheilor și semnături digitale. Este concepută pentru a facilita integrarea securității post-cuantice în protocoalele și aplicațiile existente, asigurând protecția datelor împotriva amenințărilor viitoare din partea computerelor cuantice la scară largă. Biblioteca se distinge printr-un accent pe implementări de înaltă asigurare și rezistență la atacuri side-channel, utilizând primitive de tip constant-time pentru a preveni scurgerea de informații bazată pe timp. Oferă o configurare extinsă la momentul compilării, permițând dezvoltatorilor să selecteze algoritmi specifici și să gestioneze dimensiunea binară, ceea ce permite deployment-ul în medii diverse, variind de la servere la sisteme embedded cu resurse limitate. Proiectul include instrumente cuprinzătoare pentru benchmarking-ul performanței și injectarea de entropie agnostică față de hardware, susținând utilizarea generatoarelor de numere aleatorii personalizate. De asemenea, oferă harness-uri de testare încorporate pentru verificarea execuției constant-time și evaluarea eficienței operațiunilor criptografice pe diverse arhitecturi de procesor.

    Implements constant-time memory access patterns to prevent timing-based side-channel information leakage.

    Ccryptographykey-exchange-algorithmslattice-based-crypto
    Vezi pe GitHub↗2,979
  1. Home
  2. Software Engineering & Architecture
  3. Shared Memory Management
  4. Memory Access Profilers
  5. Cache-Aware Memory Access

Explorează sub-etichetele

  • Constant-Time Memory AccessMemory access patterns that do not depend on secret data to prevent side-channel timing attacks. **Distinct from Cache-Aware Memory Access:** Distinct from cache-aware access by focusing on security and timing-attack prevention rather than performance optimization.
  • NUMA OptimizationsMemory access strategies that account for Non-Uniform Memory Access architectures to reduce remote memory requests. **Distinct from Cache-Aware Memory Access:** Specifically targets NUMA topology for latency reduction, whereas Cache-Aware Memory Access focuses on cache line alignment.
  • SIMD Buffer Padding1 sub-tagMemory allocation strategies that ensure buffers have trailing padding to support wide vector loads. **Distinct from Cache-Aware Memory Access:** Distinct from general cache-aware access: specifically addresses the padding requirement for SIMD memory safety.
  • Software PrefetchingTechniques for explicitly instructing the CPU to load data into the cache before it is needed. **Distinct from Cache-Aware Memory Access:** Distinct from Cache-Aware Memory Access: focuses on active preloading of addresses rather than static alignment or layout.