6 repository-uri
Educational resources detailing the internal design and operational cycles of central processing units.
Distinct from System Internals: None of the candidates cover physical CPU hardware architecture; they focus on software internals, interpreters, or databases.
Explore 6 awesome GitHub repositories matching operating systems & systems programming · CPU Architectures. Refine with filters or upvote what's useful.
This project is a comprehensive technical interview preparation resource and computer science interview guide. It serves as an educational reference for developers to study core software engineering fundamentals and common coding patterns required for employment screenings. The repository provides detailed guides and references covering data structures and algorithms, networking and security, operating systems, and web development. It specifically focuses on the implementation and complexity analysis of sorting, searching, and graph algorithms. The material encompasses a wide breadth of comp
An explanation of the internal components and operational cycle of a central processing unit.
Bitwise is a computer architecture education kit and a comprehensive set of guides for building a custom CPU, operating system, and compiler from scratch. It serves as a CPU design tutorial and a practical framework for implementing a unique instruction set architecture. The project provides a custom instruction set architecture toolchain, including resources for creating a matching assembler and compiler. It further includes a hardware development guide for synthesizing computer components and peripheral controllers for deployment on programmable logic devices and FPGAs. The kit covers full
Provides educational resources and logic for creating custom processor architectures for FPGA synthesis.
excelCPU este un emulator de calculator bazat pe foaie de calcul care simulează o unitate centrală de procesare (CPU) pe 16 biți. Funcționează ca un model educațional de CPU unde starea sistemului, registrele și memoria cu acces aleatoriu (RAM) sunt gestionate într-o grilă de celule de foaie de calcul. Proiectul include un compilator de limbaj de asamblare care convertește codul sursă de asamblare personalizat într-un format compatibil cu celulele foii de calcul pentru stocarea în memorie read-only. Permite atât execuția automată a programelor, cât și operarea manuală pentru a suprascrie instrucțiuni specifice. Simularea acoperă concepte de arhitectură hardware de bază, inclusiv prototiparea porților logice, preluarea instrucțiunilor și gestionarea memoriei. Acest mediu permite vizualizarea interacțiunilor dintre registre și memoria sistemului prin logică bazată pe formule.
Implements a simplified hardware architecture to demonstrate the fundamentals of machine cycles.
Asterinas is a memory-safe operating system kernel designed to prevent data races and memory corruption. It functions as a Linux-ABI compatible kernel, enabling the execution of existing Linux binaries and container workloads while providing a declarative operating system distribution model. The project distinguishes itself by acting as a virtual machine container host and a confidential computing guest OS, allowing it to run within hardware-isolated Trusted Execution Environments such as Intel TDX. It implements a minimal trusted computing base by isolating unsafe low-level operations and se
Enables selection of the target processor architecture for compilation via environment variables.
This is an open-source video player application for Android that compiles native C and C++ libraries using the Android NDK and CMake. The build system automatically discovers the Android SDK from environment variables and selects the appropriate Java runtime (8, 11, or 17) for different build tools, while allowing control over which CPU architectures (ARM, x86) to target. The application manages media libraries by scanning local storage and fetching metadata from external services to organize video files with cover art, descriptions, and series grouping. It streams video from both local devic
Controls which CPU architectures like ARM and x86 to compile native code for.
perf-ninja is a collection of educational resources and curricula focused on CPU architecture, memory hierarchies, SIMD programming, and low-level performance engineering. It provides instructional material and practical labs for identifying and fixing CPU bottlenecks, such as cache misses and branch mispredictions. The project differentiates itself through specialized training in hardware-level optimizations, including the use of compiler intrinsics for SIMD vectorization and the implementation of branchless predicate execution to eliminate pipeline stalls. It also covers advanced binary-lev
Provides a curriculum on the internal design and operational cycles of CPUs, including pipeline stalls and TLB misses.