# verilator/verilator

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3,365 stars · 754 forks · SystemVerilog · other

## Links

- GitHub: https://github.com/verilator/verilator
- Homepage: https://verilator.org
- awesome-repositories: https://awesome-repositories.com/repository/verilator-verilator.md

## Topics

`compilers` `cpp` `rtl` `system-verilog` `systemc` `verilator` `verilog` `verilog-simulator`

## Description

Verilator is a hardware simulation engine and toolchain that translates Verilog and SystemVerilog hardware description languages into optimized C++ or SystemC models. It functions as a compiler and transpiler, converting hardware designs into executable binaries to achieve high-speed simulation and integration into software environments.

The project distinguishes itself by focusing on simulation acceleration through the generation of optimized C++ classes and cycle-accurate models. It provides a SystemVerilog linter for static analysis of hardware designs and a hardware coverage analyzer to track functional and code coverage during the verification process.

The system covers a broad range of capabilities including hardware-software co-simulation via Direct Programming Interfaces and the serialization of signal activity into waveform trace files. It supports multi-threaded model execution, hierarchical verilation for large designs, and performance profiling to identify execution bottlenecks.

The toolchain allows for custom build configuration, including cross-compilation and containerized execution, and provides mechanisms for custom code injection into generated models.

## Tags

### Part of an Awesome List

- [Simulation Acceleration](https://awesome-repositories.com/f/awesome-lists/devtools/hardware-simulation/simulation-acceleration.md) — Converts Verilog and SystemVerilog designs into optimized C++ or SystemC models to achieve high-speed simulation.
- [Hardware Simulation](https://awesome-repositories.com/f/awesome-lists/devtools/hardware-simulation.md) — Provides a simulation environment that executes compiled hardware models as high-performance C++ binaries.
- [HDL Design Linting](https://awesome-repositories.com/f/awesome-lists/devtools/hdl-design-linting.md) — Analyzes hardware description code for quality issues and common design errors to prevent bugs before simulation.

### Programming Languages & Runtimes

- [Source-to-C Transpilers](https://awesome-repositories.com/f/programming-languages-runtimes/source-code-compilers/source-to-c-transpilers.md) — Translates hardware description languages into optimized C++ or SystemC models for high-speed simulation. ([source](https://verilator.org/guide/latest/languages.html))
- [HDL Compilers](https://awesome-repositories.com/f/programming-languages-runtimes/hdl-compilers.md) — Translates Verilog and SystemVerilog code into optimized C++ or SystemC models for high-speed simulation.
- [Bi-Directional Language Bridging](https://awesome-repositories.com/f/programming-languages-runtimes/language-interoperability/bi-directional-language-bridging.md) — Implements a standardized bridge for bidirectional function calls and data exchange between C++ and hardware logic.
- [Compiler-Based Instrumentation](https://awesome-repositories.com/f/programming-languages-runtimes/compiler-based-instrumentation.md) — Inserts probe points into the generated C++ model to record which logic paths are exercised during execution.
- [Hierarchical Compilation](https://awesome-repositories.com/f/programming-languages-runtimes/hierarchical-compilation.md) — Splits massive designs into smaller models to reduce memory consumption and shorten compilation times. ([source](https://verilator.org/guide/latest/verilating.html))
- [CPU Core Partitioning](https://awesome-repositories.com/f/programming-languages-runtimes/high-concurrency-runtimes/resource-allocation-groups/cpu-core-partitioning.md) — Manages memory access strategies for thread pools to prioritize physical core usage and improve runtime speed. ([source](https://verilator.org/guide/latest/environment.html))
- [Multi-threaded Execution](https://awesome-repositories.com/f/programming-languages-runtimes/language-features-paradigms/concurrency-models/concurrency/execution-models/multi-threaded-execution.md) — Distributes the evaluation of independent hardware modules across multiple CPU cores to increase simulation throughput.
- [Simulation Binary Generation](https://awesome-repositories.com/f/programming-languages-runtimes/simulation-binary-generation.md) — Produces standalone binary or library files that can be wrapped in custom code to execute design simulations.

### Development Tools & Productivity

- [Code Linters](https://awesome-repositories.com/f/development-tools-productivity/code-linters.md) — Provides a static analysis tool that scans SystemVerilog code for quality issues and common design errors.
- [Static Code Linting](https://awesome-repositories.com/f/development-tools-productivity/static-code-linting.md) — Analyzes hardware source code before compilation to detect structural errors and non-synthesizable constructs.
- [Interface Coverage Analysis](https://awesome-repositories.com/f/development-tools-productivity/cli-command-frameworks/interface-coverage-analysis.md) — Allows excluding specific blocks of hardware description code from coverage metrics to focus on relevant logic. ([source](https://verilator.org/guide/latest/extensions.html))
- [Performance and Resource Profilers](https://awesome-repositories.com/f/development-tools-productivity/debugging-profiling-testing/debugging-diagnostics/performance-resource-profilers.md) — Measures execution time and resource usage to find and resolve efficiency bottlenecks in simulations. ([source](https://verilator.org/verilator_doc.html))
- [Hardware Diagnostics](https://awesome-repositories.com/f/development-tools-productivity/integration-metadata-retrievers/hardware-metadata-retrievers/hardware-diagnostics.md) — Produces SARIF diagnostics and clock domain crossing checks to verify design quality and correctness. ([source](https://verilator.org/guide/latest/files.html))

### Hardware & IoT

- [Direct Programming Interfaces](https://awesome-repositories.com/f/hardware-iot/direct-programming-interfaces.md) — Implements the DPI standard for bidirectional function calls and data exchange between C++ and hardware logic. ([source](https://verilator.org/guide/latest/connecting.html))
- [Hardware Interfacing](https://awesome-repositories.com/f/hardware-iot/integration-performance/hardware-interfacing-integration/hardware-interfacing.md) — Connects hardware models to software environments using APIs, DPI, or VPI. ([source](https://verilator.org/verilator_doc.html))
- [Logic Waveform Analysis](https://awesome-repositories.com/f/hardware-iot/logic-waveform-analysis.md) — Generates and exports VCD or FST trace files to visualize signal activity and timing behavior during simulation.
- [Simulation Waveform Exports](https://awesome-repositories.com/f/hardware-iot/simulation-waveform-exports.md) — Generates trace files and Gantt report waveforms to visualize signal activity and timing behavior. ([source](https://verilator.org/guide/latest/files.html))
- [Constrained Random Verification](https://awesome-repositories.com/f/hardware-iot/constrained-random-verification.md) — Generates constrained random test vectors using a solver to ensure comprehensive coverage of hardware edge cases. ([source](https://verilator.org/guide/latest/install.html))
- [Hardware Signal Forcing](https://awesome-repositories.com/f/hardware-iot/hardware-signal-forcing.md) — Creates public control signals that allow C++ code to force or release specific hardware signals during simulation. ([source](https://verilator.org/guide/latest/control.html))
- [Hardware Signal Reading](https://awesome-repositories.com/f/hardware-iot/hardware-signal-reading.md) — Allows reading specific hardware signal values directly from C++ by declaring signals as public. ([source](https://verilator.org/guide/latest/faq.html))
- [Hardware Waveform Serialization](https://awesome-repositories.com/f/hardware-iot/hardware-waveform-serialization.md) — Records signal activity into VCD or FST formats by logging state changes during simulation runtime.

### Operating Systems & Systems Programming

- [Parallel Workload Distribution](https://awesome-repositories.com/f/operating-systems-systems-programming/symmetric-multiprocessing-mechanisms/parallel-workload-distribution.md) — Distributes workloads across multiple CPU threads to increase throughput and speed up trace construction. ([source](https://verilator.org/guide/latest/verilating.html))
- [Cycle-Accurate Emulators](https://awesome-repositories.com/f/operating-systems-systems-programming/virtualization-emulation/hardware-emulators/cycle-accurate-emulators.md) — Creates a software representation of hardware that simulates logic transitions at every clock tick.

### Software Engineering & Architecture

- [Hardware Timing Modeling](https://awesome-repositories.com/f/software-engineering-architecture/execution-flow-control/simulation-flow-controllers/hardware-timing-modeling.md) — Provides the ability to execute delay statements and event controls to model accurate hardware temporal behavior. ([source](https://verilator.org/guide/latest/languages.html))
- [Hardware-Software Domain Bridges](https://awesome-repositories.com/f/software-engineering-architecture/stream-component-bridging/hardware-software-domain-bridges.md) — Integrates hardware models with software environments using C++ APIs and Direct Programming Interfaces for system testing.
- [Execution Flow Visualizations](https://awesome-repositories.com/f/software-engineering-architecture/state-transition-models/visual-state-transitions/execution-flow-visualizations.md) — Records timing and task flow to generate Gantt charts and parallelism statistics for execution paths. ([source](https://verilator.org/guide/latest/simulating.html))

### Testing & Quality Assurance

- [Code Coverage Analysis](https://awesome-repositories.com/f/testing-quality-assurance/code-coverage-analysis.md) — Tracks functional and code coverage to determine which parts of a hardware design were exercised during testing.
- [State Transition Coverage](https://awesome-repositories.com/f/testing-quality-assurance/code-coverage-analysis/coverage-exclusions/state-transition-coverage.md) — Identifies transparent state-register wrappers to extract and analyze finite state machine state and transition coverage. ([source](https://verilator.org/guide/latest/control.html))
- [Functional Coverage Monitoring](https://awesome-repositories.com/f/testing-quality-assurance/functional-coverage-monitoring.md) — Monitors covergroups and transition bins to measure the verification progress of a hardware design. ([source](https://verilator.org/guide/latest/languages.html))
- [Uninitialized Logic Detection](https://awesome-repositories.com/f/testing-quality-assurance/general-bug-detection/uninitialized-logic-detection.md) — Uses random variable initialization and assignment strategies to uncover reset failures and uninitialized logic. ([source](https://verilator.org/guide/latest/languages.html))
- [Performance Profiling](https://awesome-repositories.com/f/testing-quality-assurance/performance-testing-analysis/performance-profiling.md) — Maps performance data back to original line numbers to identify and fix execution bottlenecks in source code. ([source](https://verilator.org/guide/latest/simulating.html))
- [Hardware Core Verifications](https://awesome-repositories.com/f/testing-quality-assurance/test-suite-execution/code-correctness-verifications/hardware-core-verifications.md) — Implements a verification workflow that collects code and functional coverage data to ensure design exercise.