Verilator | Awesome Repository

Verilator is a hardware simulation engine and toolchain that translates Verilog and SystemVerilog hardware description languages into optimized C++ or SystemC models. It functions as a compiler and transpiler, converting hardware designs into executable binaries to achieve high-speed simulation and integration into software environments.

The project distinguishes itself by focusing on simulation acceleration through the generation of optimized C++ classes and cycle-accurate models. It provides a SystemVerilog linter for static analysis of hardware designs and a hardware coverage analyzer to track functional and code coverage during the verification process.

The system covers a broad range of capabilities including hardware-software co-simulation via Direct Programming Interfaces and the serialization of signal activity into waveform trace files. It supports multi-threaded model execution, hierarchical verilation for large designs, and performance profiling to identify execution bottlenecks.

The toolchain allows for custom build configuration, including cross-compilation and containerized execution, and provides mechanisms for custom code injection into generated models.

Features

Simulation Acceleration - Converts Verilog and SystemVerilog designs into optimized C++ or SystemC models to achieve high-speed simulation.
Source-to-C Transpilers - Translates hardware description languages into optimized C++ or SystemC models for high-speed simulation.
Hardware Simulation - Provides a simulation environment that executes compiled hardware models as high-performance C++ binaries.
HDL Design Linting - Analyzes hardware description code for quality issues and common design errors to prevent bugs before simulation.

Features

Simulation Acceleration - Converts Verilog and SystemVerilog designs into optimized C++ or SystemC models to achieve high-speed simulation.
Source-to-C Transpilers - Translates hardware description languages into optimized C++ or SystemC models for high-speed simulation.
Hardware Simulation - Provides a simulation environment that executes compiled hardware models as high-performance C++ binaries.
HDL Design Linting - Analyzes hardware description code for quality issues and common design errors to prevent bugs before simulation.

The toolchain allows for custom build configuration, including cross-compilation and containerized execution, and provides mechanisms for custom code injection into generated models.