# infrasys-ai/aisystem

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17,017 stars · 2,404 forks · Jupyter Notebook · Apache-2.0

## Links

- GitHub: https://github.com/Infrasys-AI/AISystem
- Homepage: https://infrasys-ai.github.io/aisystem-docs/
- awesome-repositories: https://awesome-repositories.com/repository/infrasys-ai-aisystem.md

## Topics

`ai` `aiinfra` `aisys` `dlsys` `mlsys`

## Description

AISystem is a comprehensive AI full-stack infrastructure project covering the entire pipeline from AI chip architecture to high-level training frameworks. It encompasses the development of AI compiler frameworks, inference engines, and distributed training orchestrators designed to coordinate workloads across a heterogeneous compute stack of CPUs, GPUs, and NPUs.

The project focuses on the deep integration of software and hardware, employing software-hardware co-design to align tensor layouts with physical memory structures. It provides specialized capabilities for accelerating Transformer models and Mixture of Experts through dedicated engines and sparse computation acceleration.

Its broader scope includes multi-dimensional distributed parallelism for large-scale model training, high-performance inference optimization via quantization and pruning, and advanced memory management techniques such as tiled memory and unified memory spaces. It also addresses hardware interconnects and collective communication primitives to scale compute clusters.

The project is primarily implemented and documented via Jupyter Notebooks.

## Tags

### Artificial Intelligence & ML

- [Distributed Training](https://awesome-repositories.com/f/artificial-intelligence-ml/distributed-training-frameworks/distributed-training.md) — Provides a full-stack infrastructure to scale the training of large AI models using data and model parallelism. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/04Cambricon.html))
- [Large-Scale Model Training](https://awesome-repositories.com/f/artificial-intelligence-ml/large-scale-model-training.md) — Manages memory and distributed training requirements for high-parameter structures like Transformers. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/02Develop.html))
- [AI Framework Internals](https://awesome-repositories.com/f/artificial-intelligence-ml/ai-framework-internals.md) — Provides core framework components including automatic differentiation and neural network graph representations. ([source](https://infrasys-ai.github.io/aisystem-docs/_sources/index.md))
- [AI Hardware Acceleration](https://awesome-repositories.com/f/artificial-intelligence-ml/ai-hardware-acceleration.md) — Designs physical chip structures for GPUs and NPUs to optimize AI computation and memory access.
- [AI Inference Engines](https://awesome-repositories.com/f/artificial-intelligence-ml/ai-inference-engines.md) — A runtime environment that optimizes trained models through quantization and pruning for efficient deployment on cloud and edge devices.
- [Memory-Compute Overlaps](https://awesome-repositories.com/f/artificial-intelligence-ml/communication-computation-overlap/memory-compute-overlaps.md) — Hides computational latency by overlapping memory copies with execution in matrix and attention kernels. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware05Abroad/05TPU1.html))
- [Convolutional Hardware Accelerators](https://awesome-repositories.com/f/artificial-intelligence-ml/convolutional-operations/convolutional-hardware-accelerators.md) — Accelerates convolutional operations by transforming them into matrix multiplications leveraging dedicated hardware cube units. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/09AscendSOC.html))
- [Distributed Model State Management](https://awesome-repositories.com/f/artificial-intelligence-ml/distributed-model-state-management.md) — Coordinates weight updates and broadcasting across clusters using synchronous or asynchronous parameter servers. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware05Abroad/07TPU3.html))
- [Distributed Training Managers](https://awesome-repositories.com/f/artificial-intelligence-ml/distributed-training-managers.md) — Configures and scales machine learning training jobs across multiple compute nodes and hardware accelerators. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/05Sample.html))
- [Distributed Training Orchestration](https://awesome-repositories.com/f/artificial-intelligence-ml/distributed-training-orchestration.md) — A platform for scaling large-scale model training across hardware clusters using data and model parallelism.
- [Distributed Training Scaling Utilities](https://awesome-repositories.com/f/artificial-intelligence-ml/distributed-training-scaling-utilities.md) — Manages and scales training workloads across distributed AI clusters to handle massive datasets. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/02Develop.html))
- [Full-Stack AI Infrastructure](https://awesome-repositories.com/f/artificial-intelligence-ml/full-stack-ai-infrastructure.md) — A comprehensive set of technologies covering AI chips, compilers, inference engines, and training frameworks.
- [Distributed Gradient Synchronization](https://awesome-repositories.com/f/artificial-intelligence-ml/gradient-computation/distributed-gradient-synchronization.md) — Coordinates global data exchange operations to synchronize parameters and gradients across distributed process groups. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/04BasicNvlink.html))
- [Data Parallelism](https://awesome-repositories.com/f/artificial-intelligence-ml/gradient-computation/distributed-gradient-synchronization/data-parallelism.md) — Splits large datasets across multiple devices that synchronize gradients via collective communication. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/03MobileParallel.html))
- [Hardware Operator Integrations](https://awesome-repositories.com/f/artificial-intelligence-ml/hardware-operator-integrations.md) — Registers hardware-specific operator libraries into tensor libraries to enable computations on specialized accelerators. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/04Cambricon.html))
- [High Throughput Inference](https://awesome-repositories.com/f/artificial-intelligence-ml/high-throughput-inference.md) — Implements specialized kernels and attention mechanisms to maximize the number of concurrent inference requests processed per second. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/06Foundation.html))
- [Inference Execution](https://awesome-repositories.com/f/artificial-intelligence-ml/inference-execution.md) — Executes the forward propagation path of trained models to generate predictions from new data. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/02Develop.html))
- [Kernel Optimizers](https://awesome-repositories.com/f/artificial-intelligence-ml/kernel-optimizers.md) — Implements kernel optimization strategies such as on-chip memory tiling and loop transformation to maximize hardware utilization. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/05Sample.html))
- [Heterogeneous Orchestrators](https://awesome-repositories.com/f/artificial-intelligence-ml/local-model-orchestrators/heterogeneous-orchestrators.md) — Manages data movement and task scheduling across a heterogeneous compute stack of CPUs, GPUs, and NPUs.
- [Mixed Precision Training](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/machine-learning-training/distributed-and-accelerated-compute/training-acceleration-tools/mixed-precision-training.md) — Utilizes bfloat16 formats to maintain numerical stability and reduce memory overhead during large model training. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware05Abroad/04TPUIntrol.html))
- [Mixed-Precision Computing](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/machine-learning-training/distributed-and-accelerated-compute/training-acceleration-tools/mixed-precision-training/mixed-precision-computing.md) — Executes operations across multiple numerical precisions to balance computational speed and accuracy. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/README.html))
- [Inference Optimization Techniques](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/model-deployment-and-serving/inference-optimization-and-tuning/inference-optimization-techniques.md) — Describes techniques for inference engines including model pruning and computational graph optimization. ([source](https://cdn.jsdelivr.net/gh/infrasys-ai/aisystem@main/README.md))
- [Edge AI Model Deployment](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/model-deployment-and-serving/local-and-on-device-inference/edge-ai-model-deployment.md) — Optimizes and integrates machine learning models to run locally on resource-constrained mobile and IoT devices. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/06NPUBase.html))
- [Cross-Platform Deployments](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/model-deployment-and-serving/local-and-on-device-inference/edge-ai-model-deployment/cross-platform-deployments.md) — Deploys models flexibly across edge, cloud, and mobile devices using a unified architecture. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/08AscendBase.html))
- [Inference Optimization](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/model-inference-serving/inference-optimization.md) — Implements quantization, pruning, and kernel tuning to improve model execution speed and reduce memory usage for production.
- [Large Model Optimizations](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/model-optimization-and-inference/serving-and-runtime/inference-optimizations/large-model-optimizations.md) — Optimizes full-stack hardware and software performance for large-scale clusters and distributed communication. ([source](https://infrasys-ai.github.io/aisystem-docs/))
- [Model Parallelism](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/model-training-and-tuning/training-frameworks/model-training-pipelines/model-parallelism.md) — Distributes single model tensors or layers across multiple devices to support models exceeding single-chip memory. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/03MobileParallel.html))
- [Model Pruning](https://awesome-repositories.com/f/artificial-intelligence-ml/model-optimization/compression-techniques/model-pruning.md) — Removes redundant parameters from neural networks to decrease model complexity and accelerate inference. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/02ArchSlim.html))
- [Model Deployment Toolkits](https://awesome-repositories.com/f/artificial-intelligence-ml/model-optimization/inference-deployment/model-deployment-toolkits.md) — Converts trained models into optimized formats for specific runtime environments to maximize production resource efficiency. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/06Foundation.html))
- [8-Bit Inference Quantizers](https://awesome-repositories.com/f/artificial-intelligence-ml/model-quantization/8-bit-inference-quantizers.md) — Converts weights and activations to 8-bit precision to reduce memory footprint and accelerate inference. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware05Abroad/04TPUIntrol.html))
- [Memory Layout Optimizers](https://awesome-repositories.com/f/artificial-intelligence-ml/model-training-optimizers/memory-layout-optimizers.md) — Implements tensor memory layout optimizations to increase training throughput by leveraging GPU Tensor Cores. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/11AscendLayout.html))
- [Hardware Acceleration](https://awesome-repositories.com/f/artificial-intelligence-ml/model-training/hardware-acceleration.md) — Optimizes the balance between compute power, memory bandwidth, and precision to accelerate large-scale model training. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/06NPUBase.html))
- [Multi-Precision Matrix Multiplications](https://awesome-repositories.com/f/artificial-intelligence-ml/multi-precision-matrix-multiplications.md) — Executes matrix multiplications using bfloat16 and other low-precision formats for efficient acceleration. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware05Abroad/06TPU2.html))
- [Neural Network Training](https://awesome-repositories.com/f/artificial-intelligence-ml/neural-network-training.md) — Optimizes model weights via iterative cycles of forward propagation and gradient updates to minimize loss. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/02Develop.html))
- [Hardware Training Acceleration](https://awesome-repositories.com/f/artificial-intelligence-ml/neural-network-training/hardware-training-acceleration.md) — Optimizes hardware for backpropagation using high-precision formats and programmable vector units. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/05GPUBase.html))
- [Weight Quantization](https://awesome-repositories.com/f/artificial-intelligence-ml/quantized-inference-runtimes/weight-quantization.md) — Compresses high-precision floating-point weights into low-bit integer formats to reduce memory footprint and latency. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/02ArchSlim.html))
- [Tensor Operation Implementations](https://awesome-repositories.com/f/artificial-intelligence-ml/tensor-operation-implementations.md) — Performs fundamental mathematical operations on tensors, from basic arithmetic and reshapes to complex convolutional kernels. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/05Sample.html))
- [Multi-Dimensional Parallelism](https://awesome-repositories.com/f/artificial-intelligence-ml/tensor-parallelism/multi-dimensional-parallelism.md) — Splits tensors and datasets across clusters using combined data and model parallelism coordinated via collective communication.
- [Transformer Training Accelerators](https://awesome-repositories.com/f/artificial-intelligence-ml/transformer-training-accelerators.md) — Provides a dedicated engine and optimized kernels to accelerate Transformer-based architectures and Mixture of Experts models. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/02HistoryTC.html))
- [Backpropagation Training](https://awesome-repositories.com/f/artificial-intelligence-ml/weight-reconstruction/discriminator-weight-updates/backpropagation-training.md) — Implements the backpropagation process to update network weights through iterative data batch processing. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/05Sample.html))
- [Inter-Chip Network Topologies](https://awesome-repositories.com/f/artificial-intelligence-ml/ai-hardware-acceleration/chip-level-optimizations/inter-chip-network-topologies.md) — Implements 2D Torus network topologies to connect neighboring chips and reduce communication latency. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware05Abroad/07TPU3.html))
- [Chip Architecture Analyses](https://awesome-repositories.com/f/artificial-intelligence-ml/ai-hardware-explainers/chip-architecture-analyses.md) — Analyzes structural differences between CPUs, GPUs, FPGAs, and ASICs to optimize AI efficiency and power consumption. ([source](https://cdn.jsdelivr.net/gh/infrasys-ai/aisystem@main/README.md))
- [AI Workflow Orchestration](https://awesome-repositories.com/f/artificial-intelligence-ml/ai-workflow-orchestration.md) — Provides orchestration to link models with external APIs and memory modules for complex end-to-end applications. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/06Foundation.html))
- [Hardware-Aware Generation](https://awesome-repositories.com/f/artificial-intelligence-ml/context-aware-code-generators/hardware-aware-generation.md) — Generates model structures and sizes that adapt to the detected hardware specifications of the execution environment. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/08AscendBase.html))
- [Convolutional Accelerators](https://awesome-repositories.com/f/artificial-intelligence-ml/convolutional-operations/convolutional-accelerators.md) — Accelerates convolutional operations by converting them into general matrix multiplications using the Im2Col algorithm. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/01BasicTC.html))
- [Parallel](https://awesome-repositories.com/f/artificial-intelligence-ml/cpu-gpu-workload-balancing/pipeline-synchronization/parallel.md) — Coordinates execution across scalar, vector, and matrix pipelines using software-controlled synchronization. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/10AscendCube.html))
- [Hardware-Aware Operator Kernels](https://awesome-repositories.com/f/artificial-intelligence-ml/cpu-optimizations/hardware-specific-execution-optimizers/hardware-aware-operator-kernels.md) — Executes high-performance tensor and matrix operations optimized for specific hardware memory layouts. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/04Cambricon.html))
- [Data Preparation](https://awesome-repositories.com/f/artificial-intelligence-ml/data-preparation.md) — Includes utilities for collecting, cleaning, and applying human-in-the-loop labeling to create high-fidelity datasets. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/06Foundation.html))
- [External Knowledge Integrators](https://awesome-repositories.com/f/artificial-intelligence-ml/external-service-integrations/external-knowledge-integrators.md) — Integrates vector databases to store and retrieve relevant context via embeddings to augment model knowledge. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/06Foundation.html))
- [GPU-Accelerated Data Preprocessing](https://awesome-repositories.com/f/artificial-intelligence-ml/hardware-acceleration-backends/cuda-mining-backends/gpu-accelerated-training/gpu-accelerated-data-preprocessing.md) — Runs hardware-accelerated decoding and image operations on GPUs to prepare data for AI engines. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/09AscendSOC.html))
- [General Purpose Compute Backends](https://awesome-repositories.com/f/artificial-intelligence-ml/hardware-acceleration-backends/general-purpose-compute-backends.md) — Provides hardware acceleration interfaces for general-purpose numerical and scientific computing. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/05GPUBase.html))
- [Hardware-Level Format Conversions](https://awesome-repositories.com/f/artificial-intelligence-ml/hardware-target-conversions/hardware-level-format-conversions.md) — Implements high-efficiency data transformations using dedicated memory transfer units to eliminate pipeline stalls. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/10AscendCube.html))
- [Inference Model Deployment](https://awesome-repositories.com/f/artificial-intelligence-ml/inference-model-deployment.md) — Converts models from frameworks into a unified compute graph for optimized execution. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/04Cambricon.html))
- [Computing Pattern Analyses](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/machine-learning-training/distributed-and-accelerated-compute/training-acceleration-tools/mixed-precision-training/mixed-precision-computing/computing-pattern-analyses.md) — Examines AI-specific computational patterns and precision formats to optimize memory access and power efficiency. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware/README.html))
- [Matrix Fused Multiply-Add Engines](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/machine-learning-training/distributed-and-accelerated-compute/training-acceleration-tools/mixed-precision-training/mixed-precision-computing/matrix-fused-multiply-add-engines.md) — Executes high-throughput matrix multiply-accumulate operations using dedicated hardware cores. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/01BasicTC.html))
- [On-Device Training](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/model-deployment-and-serving/local-and-on-device-inference/edge-ai-model-deployment/on-device-training.md) — Enables updating local inference parameters directly on the device to improve accuracy and protect data privacy. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/08AscendBase.html))
- [Model Inference and Serving](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/model-inference-serving.md) — Deploys serialized models as high-performance services using a compatible API. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/04Cambricon.html))
- [GPU Architecture Analyses](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/model-optimization-and-inference/hardware-and-acceleration/tensor-computing-libraries/tensor-libraries/hardware-accelerated/gpu-architecture-analyses.md) — Provides architectural analysis of Tensor Cores and NVLink to optimize high-performance AI workloads. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/README.html))
- [Sparse Execution Patterns](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/model-optimization-and-inference/hardware-and-acceleration/tensor-computing-libraries/tensor-operations/sparse-tensor-representations/structured-sparsity-optimizations/sparse-execution-patterns.md) — Implements dynamic and sparse execution patterns such as Mixture of Experts to improve training efficiency. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/02Develop.html))
- [Edge Hardware Optimizations](https://awesome-repositories.com/f/artificial-intelligence-ml/machine-learning/infrastructure/model-optimization-and-inference/training-algorithms/machine-learning-optimization/ml-performance-profilers/hardware-specific-model-optimizations/edge-hardware-optimizations.md) — Optimizes model deployment for low latency and reduced power consumption on cloud and edge devices. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/06NPUBase.html))
- [Microscaling Formats](https://awesome-repositories.com/f/artificial-intelligence-ml/microscaling-formats.md) — Implements microscaling formats to reduce storage and bandwidth while maintaining precision across tensor scalars. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/02HistoryTC.html))
- [Automated Architecture Search](https://awesome-repositories.com/f/artificial-intelligence-ml/model-architecture-selection/automated-architecture-search.md) — Implements hyperparameter optimization and neural architecture search to automatically discover effective model structures. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/02Develop.html))
- [Resource-Constrained Optimizations](https://awesome-repositories.com/f/artificial-intelligence-ml/model-optimization/resource-constrained-optimizations.md) — Reduces parameter counts and operations using depthwise separable convolutions to fit models on mobile devices. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/03MobileParallel.html))
- [Edge Inference](https://awesome-repositories.com/f/artificial-intelligence-ml/neural-networks/edge-inference.md) — Executes pre-trained models directly on resource-constrained edge devices for real-time predictions. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/05GPUBase.html))
- [Sparse Computing Kernels](https://awesome-repositories.com/f/artificial-intelligence-ml/sparse-computing-kernels.md) — Implements specialized hardware cores and kernels to accelerate sparse vector and embedding operations. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware05Abroad/08TPU4.html))

### Hardware & IoT

- [Software-Hardware Co-Design](https://awesome-repositories.com/f/hardware-iot/software-hardware-co-design.md) — Jointly optimizes compiler backends and chip architectures to align tensor layouts with physical memory structures.
- [AI Hardware Connectivity Layers](https://awesome-repositories.com/f/hardware-iot/ai-hardware-connectivity-layers.md) — Links popular AI frameworks to specialized hardware through a dedicated architecture of drivers, runtimes, and compilers. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/08AscendBase.html))
- [Computational Intensity Analysis](https://awesome-repositories.com/f/hardware-iot/computational-intensity-analysis.md) — Analyzes and optimizes operational intensity to balance arithmetic operations and data transfers for maximum hardware utilization. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware03GPUBase/02Principle.html))
- [Domain-Specific AI Architectures](https://awesome-repositories.com/f/hardware-iot/domain-specific-ai-architectures.md) — Utilizes domain-specific architectures to execute large-scale matrix multiplications and convolutions efficiently. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/06NPUBase.html))
- [Hardware-Software Co-Designs](https://awesome-repositories.com/f/hardware-iot/hardware-software-co-designs.md) — Employs software-hardware co-design to align tensor layouts with physical memory structures for maximum efficiency. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/07Future.html))
- [Heterogeneous Compute Coordination](https://awesome-repositories.com/f/hardware-iot/heterogeneous-compute-coordination.md) — Integrates diverse compute units to optimize performance, power efficiency, and cost for complex workloads. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/07Future.html))
- [Heterogeneous Computing Implementations](https://awesome-repositories.com/f/hardware-iot/heterogeneous-computing-implementations.md) — Integrates multiple compute units like CPUs, GPUs, and NPUs on a single chip. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/06NPUBase.html))
- [Parallel Hierarchy Executions](https://awesome-repositories.com/f/hardware-iot/parallel-hierarchy-executions.md) — Structures parallel tasks into hierarchical grids of blocks and threads to optimize data sharing and synchronization. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware03GPUBase/03Concept.html))
- [Hardware Action Coordination](https://awesome-repositories.com/f/hardware-iot/programmable-i-o-controllers/i-o-operation-concepts/hardware-action-coordination.md) — Coordinates data movement between main memory and accelerators via CPU-controlled I/O logic. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/07Future.html))
- [Systolic Array Accelerators](https://awesome-repositories.com/f/hardware-iot/systolic-array-accelerators.md) — Uses systolic array architectures to achieve high-throughput matrix multiplication with extreme data reuse. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware05Abroad/04TPUIntrol.html))
- [Unified Computing Architectures](https://awesome-repositories.com/f/hardware-iot/unified-computing-architectures.md) — Pools disparate computing resources across different chip platforms to run applications across diverse processor types. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/07Future.html))
- [CISC Architectures](https://awesome-repositories.com/f/hardware-iot/cisc-architectures.md) — Implements CISC architecture principles using complex instructions and microcode control. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/02CPUISA.html))
- [Programming Model Mappings](https://awesome-repositories.com/f/hardware-iot/hardware-capability-modeling/programming-model-mappings.md) — Relates physical hardware structures like SIMD to software programming models such as CUDA. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware/README.html))
- [Processing Element Optimization](https://awesome-repositories.com/f/hardware-iot/processing-element-optimization.md) — Increases hardware efficiency by optimizing core counts and maximizing data reuse within processing units. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/04Metrics.html))
- [On-Chip Data Buffering](https://awesome-repositories.com/f/hardware-iot/system-on-chip-integration/on-chip-data-buffering.md) — Coordinates data movement between external memory and internal buffers to reduce power consumption. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/10AscendCube.html))
- [Tensor Layout Optimizations](https://awesome-repositories.com/f/hardware-iot/tensor-layout-optimizations.md) — Employs software-hardware co-design to align tensor layouts with physical memory structures for maximum throughput. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/11AscendLayout.html))
- [Torus-Based Compute Scaling](https://awesome-repositories.com/f/hardware-iot/torus-based-compute-scaling.md) — Interconnects TPU chips using torus topologies to create massive compute clusters. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware05Abroad/04TPUIntrol.html))
- [Torus Compute Scaling](https://awesome-repositories.com/f/hardware-iot/torus-compute-scaling.md) — Connects multiple chips using high-bandwidth interconnects to build supercomputer pods. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware05Abroad/06TPU2.html))
- [Torus Network Topologies](https://awesome-repositories.com/f/hardware-iot/torus-network-topologies.md) — Implements 3D torus parallel scaling to interconnect thousands of processing engines for high-bandwidth cluster communication. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware05Abroad/08TPU4.html))

### Programming Languages & Runtimes

- [AI Graph Compilers](https://awesome-repositories.com/f/programming-languages-runtimes/compiler-toolchain-development/ai-graph-compilers.md) — A system for translating high-level neural network graphs into optimized hardware-specific machine code and kernels.
- [AI Compiler Architectures](https://awesome-repositories.com/f/programming-languages-runtimes/compiler-interpreter-internals/compiler-toolchains/compiler-design/ai-compiler-architectures.md) — Provides detailed analysis of AI compiler architectures, including intermediate representations and backend kernel optimization. ([source](https://cdn.jsdelivr.net/gh/infrasys-ai/aisystem@main/README.md))
- [GPU Kernel Programming](https://awesome-repositories.com/f/programming-languages-runtimes/gpu-kernel-programming.md) — Writes kernels in C/C++ to execute computationally intensive tasks across a massive array of GPU threads. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware03GPUBase/03Concept.html))
- [Accelerator Kernels](https://awesome-repositories.com/f/programming-languages-runtimes/gpu-kernel-programming/accelerator-kernels.md) — Writes device-side kernels using C++ or Python to manage task partitioning and synchronization. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/04Cambricon.html))
- [Memory Hierarchy Data Movements](https://awesome-repositories.com/f/programming-languages-runtimes/memory-hierarchy-data-movements.md) — Decouples compute from data movement by asynchronously loading tensors through the memory hierarchy via software pipelining. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/02HistoryTC.html))
- [Instruction Decoding and Orchestration](https://awesome-repositories.com/f/programming-languages-runtimes/binary-instruction-execution/instruction-decoding-and-orchestration.md) — Translates binary machine code into control signals and manages the execution sequence of components. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/01CPUBase.html))
- [Asynchronous Memory Copies](https://awesome-repositories.com/f/programming-languages-runtimes/inter-level-gpu-memory-copies/asynchronous-memory-copies.md) — Moves data directly from global memory to shared memory to reduce latency and power consumption. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/02HistoryTC.html))
- [Warp Parallelism Orchestration](https://awesome-repositories.com/f/programming-languages-runtimes/warp-group-matrix-multiply-accumulates/warp-parallelism-orchestration.md) — Orchestrates warp-level thread groups to collaboratively manage matrix fragment loading and synchronization. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/03DeepTC.html))

### Data & Databases

- [Collective Communication Operations](https://awesome-repositories.com/f/data-databases/collective-communication-operations.md) — Coordinates collective communication operations across multiple chips and machines using various interconnects. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/04Cambricon.html))
- [GPU Accelerators](https://awesome-repositories.com/f/data-databases/collective-communication-operations/gpu-accelerators.md) — Optimizes high-speed data exchange between GPUs to eliminate bottlenecks in large-scale AI training. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/05DeepNvlink.html))
- [Collective GPU Communication](https://awesome-repositories.com/f/data-databases/collective-gpu-communication.md) — Implements fundamental data exchange primitives like All-reduce and Broadcast to synchronize state across nodes. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/03MobileParallel.html))
- [Tiling Strategies](https://awesome-repositories.com/f/data-databases/data-processing-pipelines/stream-processing-systems/stream-processing/memory-efficient-data-streaming/tiling-strategies.md) — Divides large matrices into smaller blocks to balance memory bandwidth and maximize hardware compute utilization. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/05Matrix.html))
- [Multi-level Caching](https://awesome-repositories.com/f/data-databases/multi-level-caching.md) — Manages a hierarchy of registers and caches to minimize data movement latency and maximize memory bandwidth. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware03GPUBase/01Works.html))
- [SIMD-Based Data Parallelism](https://awesome-repositories.com/f/data-databases/vectorized-arithmetic/simd-accelerated-arithmetic/simd-based-data-parallelism.md) — Applies a single instruction across multiple data elements simultaneously to accelerate vector operations. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/02CPUISA.html))
- [Data Processing Pipelines](https://awesome-repositories.com/f/data-databases/data-processing-pipelines.md) — Creates modular, concurrent stream processing pipelines for video decoding and image pre-processing. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/04Cambricon.html))
- [Data Path Optimizations](https://awesome-repositories.com/f/data-databases/high-throughput-data-streaming/hardware-throughput-optimization/data-path-optimizations.md) — Maximizes weight and feature ingestion using a specialized multi-input single-output hardware data path. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/10AscendCube.html))

### DevOps & Infrastructure

- [GPU and Interconnect Provisioning](https://awesome-repositories.com/f/devops-infrastructure/storage-provisioning/gpu-and-interconnect-provisioning.md) — Utilizes high-bandwidth interconnects to reduce latency and increase throughput compared to standard system buses. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/04BasicNvlink.html))
- [Multi-GPU Fabric Connectivity](https://awesome-repositories.com/f/devops-infrastructure/storage-provisioning/gpu-and-interconnect-provisioning/multi-gpu-fabric-connectivity.md) — Implements non-blocking GPU interconnects using high-speed switches to eliminate communication bottlenecks. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/06DeepNvswitch.html))
- [Compute Hardware Scaling](https://awesome-repositories.com/f/devops-infrastructure/cluster-node-management/capacity-scaling/hardware/compute-hardware-scaling.md) — Increases peak performance by expanding matrix multiplication units and implementing liquid cooling systems. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware05Abroad/07TPU3.html))
- [AI Workload Schedulers](https://awesome-repositories.com/f/devops-infrastructure/control-planes/workload-scheduling/ai-workload-schedulers.md) — Coordinates workload distribution between matrix cores and general-purpose CPUs using a dedicated AI scheduler. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/09AscendSOC.html))
- [Compute Throughput Optimizers](https://awesome-repositories.com/f/devops-infrastructure/performance-optimization-utilities/compute-throughput-optimizers.md) — Maximizes hardware utilization through massive ALU arrays and oversubscribed threading. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware03GPUBase/01Works.html))
- [Pipeline and Cache Optimizations](https://awesome-repositories.com/f/devops-infrastructure/performance-optimization-utilities/compute-throughput-optimizers/pipeline-and-cache-optimizations.md) — Reduces processing latency through the precise adjustment of clock frequencies, pipeline depth, and cache capacities. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/04CPULatency.html))

### Networking & Communication

- [AI Cluster Interconnects](https://awesome-repositories.com/f/networking-communication/cluster-network-orchestration/ai-cluster-interconnects.md) — Integrates high-speed network interfaces to scale multiple accelerators across servers for distributed training. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/09AscendSOC.html))
- [GPU Peer-to-Peer Memory Access](https://awesome-repositories.com/f/networking-communication/peer-to-peer-tunneling/gpu-peer-to-peer-memory-access.md) — Enables GPUs to read and write to the memory of other GPUs directly via RDMA for low-latency data movement. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/05DeepNvlink.html))
- [Bandwidth Scaling](https://awesome-repositories.com/f/networking-communication/cluster-network-orchestration/ai-cluster-interconnects/bandwidth-scaling.md) — Combines high-speed physical links to increase total data throughput available to each GPU. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/05DeepNvlink.html))
- [Hardware Topology Optimizers](https://awesome-repositories.com/f/networking-communication/network-topology-extensions/topology-abstraction-layers/hardware-topology-optimizers.md) — Configures physical hardware layouts, such as mesh networks, to maximize efficiency in multi-GPU clusters. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/05DeepNvlink.html))

### Operating Systems & Systems Programming

- [Systolic Array Accelerators](https://awesome-repositories.com/f/operating-systems-systems-programming/hardware-interfacing-drivers/hardware-acceleration/systolic-array-accelerators.md) — Increases throughput by mapping matrix operations to specialized accelerators using SIMD and systolic arrays. ([source](https://infrasys-ai.github.io/aisystem-docs/01Introduction/02Develop.html))
- [Remote GPU Memory Access](https://awesome-repositories.com/f/operating-systems-systems-programming/remote-gpu-memory-access.md) — Transfers data between memory regions across different nodes using RDMA to bypass the CPU. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/04BasicNvlink.html))
- [SIMT Execution Models](https://awesome-repositories.com/f/operating-systems-systems-programming/simt-execution-models.md) — Maps software threads to hardware using the Single Instruction, Multiple Threads (SIMT) execution model. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware03GPUBase/01Works.html))
- [Instruction Execution Models](https://awesome-repositories.com/f/operating-systems-systems-programming/computer-architecture/instruction-execution-models.md) — Provides analysis and implementation of how hardware processes the sequential flow of program instructions. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/01CPUBase.html))
- [Instruction Set Standardization](https://awesome-repositories.com/f/operating-systems-systems-programming/computer-architecture/instruction-execution-models/instruction-set-standardization.md) — Defines the standard interface between hardware and software through binary instruction formats and registers. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/02CPUISA.html))
- [Neural Network Instruction Execution](https://awesome-repositories.com/f/operating-systems-systems-programming/computer-architecture/instruction-execution-models/neural-network-instruction-execution.md) — Processes a specialized instruction set to handle weight loading and matrix multiplication. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware05Abroad/05TPU1.html))
- [RISC Architectures](https://awesome-repositories.com/f/operating-systems-systems-programming/computer-architecture/risc-architectures.md) — Implements RISC architecture principles using simplified, fixed-length instructions for execution efficiency. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/02CPUISA.html))
- [GPU Resource Virtualization](https://awesome-repositories.com/f/operating-systems-systems-programming/gpu-resource-virtualization.md) — Divides physical GPU hardware into isolated virtual GPUs to ensure predictable throughput across tasks. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware03GPUBase/04History.html))
- [Hardware Resource Abstractions](https://awesome-repositories.com/f/operating-systems-systems-programming/hardware-interfacing-drivers/hardware-abstraction-layers/compute-resource-selectors/hardware-resource-abstractions.md) — Abstracts hardware resources to allow developers to focus on functionality without manual configuration. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/03MobileParallel.html))
- [Physical Address Routing](https://awesome-repositories.com/f/operating-systems-systems-programming/kernel-core-internals/process-and-memory-management/memory-management-systems/physical-address-mapping/physical-address-routing.md) — Minimizes latency by transferring data between GPUs using physical memory addresses to bypass virtual translation. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/06DeepNvswitch.html))
- [MIMD Data Processing](https://awesome-repositories.com/f/operating-systems-systems-programming/mimd-data-processing.md) — Runs multiple independent instruction streams on multiple data sets across memory systems. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/02CPUISA.html))
- [On-Chip Buffering](https://awesome-repositories.com/f/operating-systems-systems-programming/shared-memory-management/on-chip-buffering.md) — Stores data in high-speed, on-chip memory buffers to reduce global memory latency. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware03GPUBase/04History.html))
- [Streaming Multiprocessor Interconnects](https://awesome-repositories.com/f/operating-systems-systems-programming/shared-memory-management/streaming-multiprocessor-interconnects.md) — Enables multiple streaming multiprocessors to access shared memory through a hardware interconnect. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/02HistoryTC.html))
- [Hardware Data Buffering](https://awesome-repositories.com/f/operating-systems-systems-programming/terminal-command-line-environments/terminal-interface-systems/terminal-output/high-speed-renderers/hardware-data-buffering.md) — Uses specialized registers to store instructions and results to reduce latency between processor and memory. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/01CPUBase.html))
- [Automatic Address Space Migration](https://awesome-repositories.com/f/operating-systems-systems-programming/virtual-memory-management/automatic-address-space-migration.md) — Moves data between CPU and GPU virtual address spaces automatically to simplify programming for large datasets. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware03GPUBase/04History.html))
- [Warp-Level Matrix Multiply-Accumulates](https://awesome-repositories.com/f/operating-systems-systems-programming/warp-level-primitives/warp-level-matrix-multiply-accumulates.md) — Generates warp-level instructions for tensor core matrix multiply-accumulate operations using specialized APIs. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/03DeepTC.html))
- [Warp-Level Matrix Scheduling](https://awesome-repositories.com/f/operating-systems-systems-programming/warp-level-primitives/warp-level-matrix-scheduling.md) — Coordinates thread groups to manage multiple hardware cores for the execution of large matrix blocks. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/01BasicTC.html))

### Scientific & Mathematical Computing

- [Tile-Based Matrix Multiplications](https://awesome-repositories.com/f/scientific-mathematical-computing/generalized-matrix-multiplications/tile-based-matrix-multiplications.md) — Segments large matrices into smaller blocks that fit into hardware processing limits for parallel execution. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/03DeepTC.html))
- [GPU Tensor Core Accelerations](https://awesome-repositories.com/f/scientific-mathematical-computing/numerical-mathematical-foundations/linear-algebra/sparse-linear-algebra-routines/block-sparse-engines/tensor-contractions/gpu-tensor-core-accelerations.md) — Uses specialized hardware units to perform high-performance mixed-precision matrix multiplication. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware03GPUBase/02Principle.html))
- [Precision Format Management](https://awesome-repositories.com/f/scientific-mathematical-computing/tensor-data-management/precision-format-management.md) — Handles various numerical precisions to balance computational speed and numerical range. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/02ArchSlim.html))
- [Unified Memory Systems](https://awesome-repositories.com/f/scientific-mathematical-computing/unified-memory-systems.md) — Eliminates redundant data copies by allowing processors to access a unified memory pool. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/07Future.html))
- [Sparse Matrix Multiplications](https://awesome-repositories.com/f/scientific-mathematical-computing/generalized-matrix-multiplications/sparse-matrix-multiplications.md) — Optimizes efficiency by utilizing specialized hardware paths to skip zero-value elements in sparse matrices. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware04NVIDIA/02HistoryTC.html))
- [Vectorized Operations](https://awesome-repositories.com/f/scientific-mathematical-computing/vectorized-operations.md) — Implements high-performance element-wise calculations on vectors using SIMD and multiple precisions. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/10AscendCube.html))

### Software Engineering & Architecture

- [Host-Device Synchronization](https://awesome-repositories.com/f/software-engineering-architecture/task-scheduling/host-device-synchronization.md) — Manages data transfer and program flow between the CPU and GPU to offload parallel workloads. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware03GPUBase/03Concept.html))
- [Hardware Abstraction Layers](https://awesome-repositories.com/f/software-engineering-architecture/cross-platform-architectures/hardware-abstraction-layers.md) — Implements abstraction layers to decouple software from physical hardware for cross-platform execution. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/07Future.html))
- [Graph Transformation Optimizations](https://awesome-repositories.com/f/software-engineering-architecture/execution-graphs/graph-execution-compilers/compiler-intermediate-representations/graph-transformation-optimizations.md) — Transforms compute graphs through operator fusion and layout conversion to maximize hardware utilization.
- [Construction and Tuning](https://awesome-repositories.com/f/software-engineering-architecture/headless-runtimes/inference-engines/construction-and-tuning.md) — Implements inference systems including model quantization, compression, and kernel-level performance tuning. ([source](https://infrasys-ai.github.io/aisystem-docs/))
- [Bus Utilization Optimizations](https://awesome-repositories.com/f/software-engineering-architecture/memory-management-utilities/memory-coalescing-utilities/bus-utilization-optimizations.md) — Employs loop unrolling and parallel execution to keep the memory bus busy and prevent processor idling during fetches. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware03GPUBase/01Works.html))
- [Data Layout Optimizations](https://awesome-repositories.com/f/software-engineering-architecture/performance-reliability/performance-optimization/computational-efficiency/computational-graph-optimizers/data-layout-optimizations.md) — Analyzes compute graphs to determine and insert efficient data layouts for optimized hardware performance. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/11AscendLayout.html))
- [Tiled Memory Access Patterns](https://awesome-repositories.com/f/software-engineering-architecture/shared-memory-management/memory-access-profilers/tiled-memory-access-patterns.md) — Divides large matrices into smaller blocks that fit into on-chip buffers to balance memory bandwidth and throughput.
- [Bandwidth Maximization](https://awesome-repositories.com/f/software-engineering-architecture/shared-memory-management/memory-access-profilers/tiled-memory-access-patterns/memory-access-pattern-optimizers/bandwidth-maximization.md) — Uses high-bandwidth memory and on-chip buffers to reduce movement latency and minimize external memory access for large parameters. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware06Domestic/09AscendSOC.html))
- [Compute Paradigm Analyses](https://awesome-repositories.com/f/software-engineering-architecture/software-architecture-patterns/paradigm-comparisons/compute-paradigm-analyses.md) — Contrasts traditional algorithmic processing with AI-specific patterns that prioritize high-density memory access. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/01Introduction.html))
- [Tensor Rearrangements](https://awesome-repositories.com/f/software-engineering-architecture/sorting-algorithms/array-rearrangement-algorithms/tensor-rearrangements.md) — Provides dedicated hardware acceleration for tensor operations such as transposition and reduction. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware05Abroad/06TPU2.html))

### Graphics & Multimedia

- [Memory Latency Hiding Loads](https://awesome-repositories.com/f/graphics-multimedia/graphics-engines-rendering/tile-map-renderers/viewport-aware-tiling/asynchronous-tile-loading/memory-latency-hiding-loads.md) — Hides memory latency by maintaining a high volume of available threads to keep processors busy during data transfers. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware03GPUBase/01Works.html))

### System Administration & Monitoring

- [Automatic Hardware Bottleneck Detectors](https://awesome-repositories.com/f/system-administration-monitoring/gpu-resource-monitoring/general-resource-bottleneck-detection/automatic-hardware-bottleneck-detectors.md) — Identifies whether performance is limited by compute throughput or memory bandwidth using hardware metrics. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/03CPUData.html))
- [Latency Measurement](https://awesome-repositories.com/f/system-administration-monitoring/hardware-performance-monitoring/latency-measurement.md) — Implements tools for measuring and modeling precise architectural memory and cache access times. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware02ChipBase/04CPULatency.html))
- [Compute Capacity Metrics](https://awesome-repositories.com/f/system-administration-monitoring/performance-monitoring-tools/compute-capacity-metrics.md) — Quantifies computational complexity and hardware speed using industry-standard TOPS and FLOPs metrics. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/04Metrics.html))
- [System Efficiency Optimizers](https://awesome-repositories.com/f/system-administration-monitoring/system-efficiency-optimizers.md) — Evaluates trade-offs between throughput, latency, and power to optimize chip selection for AI scenarios. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/04Metrics.html))

### Testing & Quality Assurance

- [Hardware Performance Benchmarking](https://awesome-repositories.com/f/testing-quality-assurance/hardware-performance-benchmarking.md) — Evaluates hardware performance limits and identifies memory or compute bottlenecks using the Roofline Model. ([source](https://infrasys-ai.github.io/aisystem-docs/02Hardware01Foundation/04Metrics.html))