# google/skywater-pdk **Attribution required: if you use, quote, or summarise this content, you must credit and link back to [awesome-repositories.com](https://awesome-repositories.com/repository/google-skywater-pdk).** 3,425 stars · 449 forks · Python · apache-2.0 ## Links - GitHub: https://github.com/google/skywater-pdk - Homepage: https://skywater-pdk.rtfd.io - awesome-repositories: https://awesome-repositories.com/repository/google-skywater-pdk.md ## Topics `asic` `asic-library` `eda` `magic` `openram` `openroad` `pdk` `skywater` ## Description The SkyWater Open-Source PDK is a fully open-source process design kit for semiconductor manufacturing, targeting the SkyWater 130nm CMOS technology node. It provides the foundational files and models needed to design and fabricate custom chips without proprietary vendor tools or foundry agreements, supporting both analog and digital design flows. This PDK includes a complete set of standard cells, I/O libraries, and design rules specific to the 130nm process, along with transistor models and verification decks. It offers a standardized framework for chip design with a tool-interface abstraction layer that decouples PDK data from specific EDA tool implementations, enabling use with both open-source and commercial tools. The project provides verification capabilities including design rule checking for layout manufacturability, layout-versus-schematic comparison to confirm electrical connectivity, and parasitic extraction for accurate post-layout simulation. It also supports SPICE-based analog circuit simulation and defines the semiconductor layer stack with physical and logical layer specifications. ## Tags ### Hardware & IoT - [Open-Source Process Design Kits](https://awesome-repositories.com/f/hardware-iot/open-source-process-design-kits.md) — Provides a fully open-source process design kit for semiconductor manufacturing with standardized file formats and tool interfaces. - [130nm CMOS Technology PDKs](https://awesome-repositories.com/f/hardware-iot/130nm-cmos-technology-pdks.md) — Provides a process design kit targeting the 130nm CMOS node, including transistor models, layout rules, and verification decks. - [Layout-Versus-Schematic Verifiers](https://awesome-repositories.com/f/hardware-iot/layout-versus-schematic-verifiers.md) — Provides layout-versus-schematic verification to confirm electrical connectivity matches the intended circuit design. - [Parasitic Extraction Frameworks](https://awesome-repositories.com/f/hardware-iot/parasitic-extraction-frameworks.md) — Extracts parasitic resistance and capacitance from completed chip layouts for accurate post-layout simulation results. - [Physical Design-Rule Checkers](https://awesome-repositories.com/f/hardware-iot/physical-design-rule-checkers.md) — Verifies chip layouts against manufacturing design rules using open-source tools to ensure foundry compliance. - [Semiconductor Layer Stack Definitions](https://awesome-repositories.com/f/hardware-iot/semiconductor-layer-stack-definitions.md) — Defines the physical and logical semiconductor layer stack for the SkyWater 130nm process. - [Semiconductor Process Design Kits](https://awesome-repositories.com/f/hardware-iot/semiconductor-process-design-kits.md) — Provides a collection of files and models that define the SkyWater 130nm semiconductor manufacturing process for chip design and fabrication. - [SkyWater 130nm PDKs](https://awesome-repositories.com/f/hardware-iot/skywater-130nm-pdks.md) — Provides the foundational PDK for the SkyWater 130nm open-source semiconductor process, supporting analog and digital design flows. - [Standard-Cell Library Abstractions](https://awesome-repositories.com/f/hardware-iot/standard-cell-library-abstractions.md) — Encapsulates standard-cell logic gates and memory elements with characterized timing and power models for digital design flows. ### Part of an Awesome List - [SPICE-Based Analog Simulators](https://awesome-repositories.com/f/awesome-lists/devtools/circuit-simulators/spice-based-analog-simulators.md) — Provides SPICE-based analog circuit simulation capabilities for verifying circuit behavior against the SkyWater 130nm process. ([source](https://skywater-pdk.rtfd.io/sim/ngspice.html)) - [SPICE-Netlist Simulation Pipelines](https://awesome-repositories.com/f/awesome-lists/devtools/circuit-simulators/spice-netlist-simulation-pipelines.md) — Runs analog circuit simulations by processing SPICE netlists through a circuit simulator for pre-manufacturing verification. ### DevOps & Infrastructure - [Physical Design Rule Checks](https://awesome-repositories.com/f/devops-infrastructure/tiling-window-managers/layout-rule-automations/physical-design-rule-checks.md) — Provides automated design rule checking for chip layouts to ensure manufacturability against process rules. ([source](https://skywater-pdk.rtfd.io/verification/drc/klayout.html)) ### Software Engineering & Architecture - [EDA Tool](https://awesome-repositories.com/f/software-engineering-architecture/abstraction-layers/eda-tool.md) — Provides standardized file formats and API bindings that decouple PDK data from specific EDA tool implementations. - [Manufacturing Rule Verifications](https://awesome-repositories.com/f/software-engineering-architecture/contextual-validation-rules/dynamic-validation-rules/rule-injection/manufacturing-rule-verifications.md) — Runs design rule checks on chip layouts using a commercial verification tool for foundry compliance. ([source](https://skywater-pdk.rtfd.io/verification/drc/calibre.html)) - [Semiconductor Design-Rule Checkers](https://awesome-repositories.com/f/software-engineering-architecture/rule-configuration-engines/rule-execution-engines/semiconductor-design-rule-checkers.md) — Provides design rule checking engines that verify chip layout manufacturability against the SkyWater 130nm process rules. ### User Interface & Experience - [Netlist Comparison Verifications](https://awesome-repositories.com/f/user-interface-experience/layout-rendering-utilities/layout-verification-tools/netlist-comparison-verifications.md) — Compares chip layouts against netlists to confirm electrical connectivity matches the intended circuit design. ([source](https://skywater-pdk.rtfd.io/verification/lvs/magic.html)) - [Post-Layout Parasitic Extractions](https://awesome-repositories.com/f/user-interface-experience/layout-rendering-utilities/layout-verification-tools/post-layout-parasitic-extractions.md) — Extracts parasitic resistance and capacitance from completed chip layouts for accurate post-layout simulation. ([source](https://skywater-pdk.rtfd.io/verification/pex/magic.html)) ### Testing & Quality Assurance - [Process Limit Verifications](https://awesome-repositories.com/f/testing-quality-assurance/process-limit-verifications.md) — Verifies that designed structure resistance falls within specified process limits to ensure manufacturability. ([source](https://skywater-pdk.rtfd.io/rules/rcx.html))