google/skywater-pdk

Features

• Open-Source Process Design Kits - Provides a fully open-source process design kit for semiconductor manufacturing with standardized file formats and tool interfaces.
• SPICE-Based Analog Simulators - Provides SPICE-based analog circuit simulation capabilities for verifying circuit behavior against the SkyWater 130nm process.
• SPICE-Netlist Simulation Pipelines - Runs analog circuit simulations by processing SPICE netlists through a circuit simulator for pre-manufacturing verification.
• Physical Design Rule Checks - Provides automated design rule checking for chip layouts to ensure manufacturability against process rules.
• 130nm CMOS Technology PDKs - Provides a process design kit targeting the 130nm CMOS node, including transistor models, layout rules, and verification decks.
• Layout-Versus-Schematic Verifiers - Provides layout-versus-schematic verification to confirm electrical connectivity matches the intended circuit design.
• Parasitic Extraction Frameworks - Extracts parasitic resistance and capacitance from completed chip layouts for accurate post-layout simulation results.
• Physical Design-Rule Checkers - Verifies chip layouts against manufacturing design rules using open-source tools to ensure foundry compliance.
• Semiconductor Layer Stack Definitions - Defines the physical and logical semiconductor layer stack for the SkyWater 130nm process.
• Semiconductor Process Design Kits - Provides a collection of files and models that define the SkyWater 130nm semiconductor manufacturing process for chip design and fabrication.
• SkyWater 130nm PDKs - Provides the foundational PDK for the SkyWater 130nm open-source semiconductor process, supporting analog and digital design flows.
• Standard-Cell Library Abstractions - Encapsulates standard-cell logic gates and memory elements with characterized timing and power models for digital design flows.
• EDA Tool - Provides standardized file formats and API bindings that decouple PDK data from specific EDA tool implementations.
• Manufacturing Rule Verifications - Runs design rule checks on chip layouts using a commercial verification tool for foundry compliance.
• Semiconductor Design-Rule Checkers - Provides design rule checking engines that verify chip layout manufacturability against the SkyWater 130nm process rules.
• Netlist Comparison Verifications - Compares chip layouts against netlists to confirm electrical connectivity matches the intended circuit design.
• Post-Layout Parasitic Extractions - Extracts parasitic resistance and capacitance from completed chip layouts for accurate post-layout simulation.
• Process Limit Verifications - Verifies that designed structure resistance falls within specified process limits to ensure manufacturability.

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