13 repositorios
Aligns data structures and access patterns to hardware cache lines to prevent performance degradation from frequent main memory fetches.
Distinct from Memory Access Profilers: Distinct from Memory Access Profilers: focuses on active data alignment and access pattern optimization rather than passive profiling.
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simdjson is a high-performance JSON parser that utilizes SIMD instructions to process gigabytes of data per second. It functions as a SIMD JSON parser, a multithreaded NDJSON processing library, a UTF-8 validation engine, and a tool for JSON minification and string building. The project focuses on high-throughput data processing, enabling the ingestion of massive JSON volumes and the verification of UTF-8 encoding standards. It includes dedicated capabilities for constructing JSON strings with optimized memory usage and removing unnecessary whitespace from documents to reduce file size. The
Allocates extra space at the end of buffers to allow wide SIMD loads without memory access violations.
The Disruptor is a lock-free inter-thread messaging library and high-performance event bus. It implements a concurrent ring buffer designed for high-concurrency and low-latency message sequencing. The project utilizes a specific messaging architecture to eliminate lock contention, enabling high-throughput event routing and the exchange of continuous event streams between threads. It ensures strict first-in-first-out ordering and immediate data visibility across processing threads. The library provides capabilities for lock-free data streaming, sequential data ordering, and sequence-based eve
Implements cache-line padding to eliminate false sharing and maximize CPU cache efficiency.
This project serves as an educational resource for learning and implementing low-level assembly language optimizations. It provides a structured guide for developers to master hardware-specific instructions and manual performance tuning, focusing on the translation of high-level code into efficient machine-level operations for resource-constrained environments. The materials emphasize techniques for maximizing computational throughput in multimedia processing. By covering instruction-level parallelism, register management, and data parallelism, the project enables the development of software
Aligns data structures and access patterns to hardware cache lines to prevent performance degradation from frequent main memory fetches.
This project is a collection of educational resources and technical guides focused on Go performance optimization. It provides instruction on improving execution speed and reducing memory usage through code and architectural refinements. The guides cover advanced strategies for low-level programming, including the use of assembly for SIMD instructions and unsafe pointers for direct memory manipulation. It also details concurrency optimization techniques such as lock sharding and cache-line padding to reduce contention and improve hardware utilization. The material encompasses broad capabilit
Implements cache-line padding to prevent false sharing and reduce CPU cache coherence traffic.
xxHash is a high-performance, non-cryptographic hash library designed for rapid checksum generation and data integrity verification. It functions as an incremental hashing engine, allowing for the processing of large or streaming data inputs by maintaining a persistent internal state across sequential chunks. The library is engineered as a computational framework that maximizes throughput by utilizing wide CPU registers and branchless instruction pipelining. It achieves high-speed performance by aligning data access with CPU cache lines and employing multi-stage mixing functions that ensure c
Optimizes memory throughput by structuring data access patterns to fit within the CPU cache lines for faster retrieval.
DeepEP is a distributed model accelerator and expert-parallel communication library designed to optimize the training and inference of large-scale neural networks. It provides specialized GPU communication kernels and a remote GPU memory interface to facilitate high-throughput data exchange between hardware nodes. The system utilizes dynamic kernel generation to compile optimized GPU kernels during execution, removing the need for separate installation compilation steps. It implements virtual-lane traffic isolation to prevent interference between different data streams and employs routing met
Utilizes low-level memory primitives to coordinate distributed parallelism and optimize hardware resource usage.
Este proyecto es un generador de ID único distribuido diseñado para producir identificadores únicos y ordenables globalmente de 64 bits a través de múltiples nodos. Implementa un algoritmo compatible con Snowflake que evita colisiones combinando marcas de tiempo, identificadores de trabajador y números de secuencia en un solo entero. El sistema incluye un orquestador de ID de trabajador para asignar y mantener identidades de máquina únicas durante el inicio y la migración de instancias utilizando estrategias respaldadas por bases de datos. Para aumentar el rendimiento de las solicitudes y reducir la latencia, utiliza una capa de caché de búfer circular que pre-genera identificadores y emplea un mecanismo de recarga basado en umbrales. El software proporciona capacidades para gestionar claves de bases de datos distribuidas, coordinar nodos del sistema y configurar la distribución de bits para equilibrar las necesidades de concurrencia frente a la vida útil del sistema. También incluye utilidades para analizar los identificadores generados de vuelta a sus componentes originales.
Employs cache-line padding between buffer elements to eliminate false sharing and increase hardware throughput.
Esta es una implementación criptográfica de la función de memoria dura Argon2, que sirve como biblioteca de hashing de contraseñas y función de derivación de claves. Transforma contraseñas y sales en hashes seguros y genera claves criptográficas diseñadas para resistir ataques de cracking de hardware de alta velocidad. La biblioteca utiliza un diseño de memoria dura que requiere una cantidad significativa de RAM para evitar la aceleración mediante GPUs o ASICs. Incorpora acceso a memoria independiente de los datos para bloquear ataques de temporización de canal lateral y admite la integración de claves secretas o peppers para proteger contra ataques de fuerza bruta en sales comprometidas. Las capacidades adicionales incluyen la codificación de hash de contraseñas para almacenamiento y transporte, la capacidad de vincular hashes a datos de contexto específicos y una gestión de memoria segura que limpia los búferes sensibles inmediatamente después de su uso.
Employs data-independent memory access patterns to block side-channel timing attacks.
This project is a technical curriculum and set of educational resources focused on parallel programming, high-performance computing, and systems programming. It provides a structured course covering the implementation of parallel algorithms and multithreading techniques for processing large datasets. The project includes a systems programming guide for modern language features, a framework for lock-free concurrency patterns, and a manual for optimizing CPU and GPU performance through assembly analysis and cache management. The material covers hardware performance tuning, the implementation o
Provides techniques for aligning data structures and access patterns to maximize CPU cache hits.
Este proyecto es una referencia técnica y una colección de notas de análisis interno centradas en el runtime y compilador del lenguaje Go. Proporciona un desglose detallado de los aspectos internos del lenguaje, cubriendo la gestión de memoria, la recolección de basura (garbage collection) y el modelo de ejecución del programador. El material se distingue por proporcionar inmersiones profundas en detalles del sistema de bajo nivel, incluyendo una referencia para instrucciones de ensamblador de Go, uso de registros e interfaz de llamadas al sistema. Analiza específicamente la implementación interna de primitivas de concurrencia, como el mecanismo de programación de goroutines, operaciones de canales e implementaciones de bloqueos de mutex. La cobertura se extiende a la teoría de construcción de compiladores, incluyendo análisis léxico y sintáctico, así como la mecánica del sistema de tipos y la gestión de interfaces. También detalla varias técnicas de optimización de rendimiento, utilidades de diagnóstico de runtime para rastreo de pila (stack tracing) y primitivas de E/S de red.
Details the use of padding bytes to prevent CPU cache coherence traffic caused by false sharing.
JCTools is a Java concurrency library providing a collection of lock-less and wait-free data structures. It serves as a toolkit for managing thread-safe data exchange, specifically designed to optimize high-throughput messaging and producer-consumer patterns in multi-threaded applications. The library distinguishes itself by implementing specialized queue structures that minimize contention and maximize throughput. By utilizing techniques such as cache-line padding, memory-barrier-based synchronization, and relaxed-consistency memory ordering, it avoids the performance bottlenecks often assoc
Aligns data structures to CPU cache lines to prevent false sharing and performance degradation in concurrent environments.
perf-ninja is a collection of educational resources and curricula focused on CPU architecture, memory hierarchies, SIMD programming, and low-level performance engineering. It provides instructional material and practical labs for identifying and fixing CPU bottlenecks, such as cache misses and branch mispredictions. The project differentiates itself through specialized training in hardware-level optimizations, including the use of compiler intrinsics for SIMD vectorization and the implementation of branchless predicate execution to eliminate pipeline stalls. It also covers advanced binary-lev
Teaches how to align data structures to cache line boundaries and implement loop tiling to minimize cache misses.
Liboqs es una biblioteca en C que proporciona una interfaz unificada para algoritmos criptográficos resistentes a la computación cuántica, incluyendo encapsulación de claves y mecanismos de firma digital. Está diseñada para facilitar la integración de la seguridad post-cuántica en protocolos y aplicaciones existentes, asegurando la protección de datos contra futuras amenazas de computadoras cuánticas a gran escala. La biblioteca se distingue por un enfoque en implementaciones de alta seguridad y resistencia a canales laterales, utilizando primitivas de tiempo constante para evitar la fuga de información basada en el tiempo. Ofrece una configuración extensa en tiempo de compilación, permitiendo a los desarrolladores seleccionar algoritmos específicos y gestionar el tamaño del binario, lo que permite el despliegue en diversos entornos que van desde servidores hasta sistemas embebidos con recursos limitados. El proyecto incluye herramientas integrales para pruebas de rendimiento e inyección de entropía agnóstica al hardware, apoyando el uso de generadores de números aleatorios personalizados. También proporciona arneses de prueba incorporados para verificar la ejecución en tiempo constante y evaluar la eficiencia de las operaciones criptográficas a través de varias arquitecturas de procesador.
Implements constant-time memory access patterns to prevent timing-based side-channel information leakage.