misprit7/computerraria
Computerraria
Computerraria is a digital logic circuit simulator and computer architecture educational tool. It provides a sandbox environment for building and testing functional computer systems by connecting modular logic gates and electronic wires.
The project serves as a RISC-V architecture simulator that executes RV32I machine code using virtualized hardware components. It includes a virtualized CPU toolchain that uses containerized systems to compile source code into binary formats compatible with these custom processor architectures.
The system covers digital logic circuit design and RISC-V ISA simulation, allowing for the verification of CPU compliance by comparing execution results against a reference simulator. It also includes capabilities for uploading and controlling binary files through a command line wrapper.
Features
- Logic Circuit Simulation - Provides an interactive environment to simulate the behavior of digital logic gates and wiring.
- Computer Architecture - Serves as a visual educational tool for observing how instructions translate into electronic signals in a simulated CPU.
- Computer Systems Education - Provides an educational environment for learning computing fundamentals by building a full hardware stack from logic gates.
- RISC-V Hardware Emulation - Simulates RISC-V hardware architectures to execute and verify RV32I machine code binaries.
- RISC-V Instruction Virtualization - Simulates the RISC-V instruction set by mapping machine code operations to virtual hardware operations.
- Machine Code Execution Engines - Runs low-level machine instructions through simulated logic components to perform general-purpose computation.
- Hardware Building Blocks - Builds complex computational systems by linking independent, reusable electronic building blocks within a sandbox.
- Containerized Toolchains - Ships a containerized toolchain to ensure consistent compilation of source code for the custom virtual processor.
- Toolchain Virtualization - Uses virtualized environments to provide a consistent toolchain for compiling code into custom processor binaries.
- Source-to-Binary Compilation Toolchains - Provides a toolchain that transforms source code into executable binaries compatible with the custom virtual processor.
- Compliance Verifiers - Validates that the simulated CPU conforms to the RISC-V technical specification through automated tests.
- Reference Implementation Validation - Validates simulated processor outputs by comparing them against a trusted software reference implementation.
