Verilog hardware description
For an open source tool for Verilog development, the strongest matches are yosyshq/yosys (Yosys is a comprehensive RTL synthesis and formal verification), enjoy-digital/litex (LiteX is a powerful SoC builder framework that automates) and chipsalliance/chisel (Chisel is a hardware construction language that generates Verilog). chipsalliance/rocket-chip and verilator/verilator round out the shortlist. Each is ranked by relevance to your query, popularity and recent activity.
Explore the best open-source Verilog tools and libraries. We ranked top hardware description projects by activity and stars to help you pick the right one.
Verilog hardware description
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- yosyshq/yosys
YosysHQ/yosys
4,543Auf GitHub ansehenYosys is a digital logic synthesizer and RTL synthesis tool that transforms hardware description language code into optimized gate-level representations. It functions as a hardware logic optimizer and formal verification tool, providing a framework to convert generic circuit representations into specific technology library cells for targeted hardware platforms. The project serves as a hardware design automator through a scriptable environment used to execute sequences of synthesis commands. This automation allows for the management of complex digital hardware workflows, integrating RTL design
Yosys is a comprehensive RTL synthesis and formal verification framework that serves as a core component of the open-source hardware toolchain, though it focuses on synthesis and optimization rather than providing a built-in Verilog simulator or waveform viewer.
C++Logic Synthesis Tools - enjoy-digital/litex
enjoy-digital/litex
3,963Auf GitHub ansehenLiteX is an FPGA SoC development suite and SoC builder framework used to programmatically design system-on-chips. It provides a hardware description toolchain that uses a scriptable framework to define hardware layouts and automate the generation of hardware description language code. The project distinguishes itself by orchestrating multiple vendor and open-source toolchains to synthesize digital logic and generate deployable bitstreams. It supports multi-language logic integration, allowing disparate hardware description languages to be combined into a single project. The framework covers
LiteX is a powerful SoC builder framework that automates the generation of hardware description code and orchestrates the synthesis toolchain, making it a highly capable tool for FPGA development even though it uses Python as a meta-language to generate the underlying HDL.
PythonBitstream Generation - chipsalliance/chisel
chipsalliance/chisel
4,691Auf GitHub ansehenChisel is a hardware construction language and description tool used to define digital circuits. It functions as a generator that converts high-level hardware descriptions into synthesizable Verilog code for use in ASIC and FPGA design. The project enables the creation of parameterizable hardware templates and reusable digital components. It leverages functional and object-oriented programming patterns to transform complex circuit representations into finalized hardware descriptions. The toolset covers the register-transfer level design workflow, allowing users to model digital circuits usin
Chisel is a hardware construction language that generates Verilog for synthesis and design, serving as a powerful alternative to writing Verilog directly while integrating into standard FPGA and ASIC toolchains.
ScalaDigital Circuit ConstructionHardware Construction LanguagesAutomated Hardware Generation - chipsalliance/rocket-chip
chipsalliance/rocket-chip
3,798Auf GitHub ansehenRocket-chip is a framework for the parametric design, synthesis, and verification of RISC-V based processors and system-on-chip hardware. It functions as a generator that converts high-level specifications into synthesizable Verilog files for FPGA or ASIC implementation. The project utilizes a Scala-based hardware description framework to produce customizable pipelined processor cores, memory hierarchies, and peripheral devices. It employs a parameter-driven model and a two-phase negotiation process to resolve hardware interface specifications between modules during the elaboration phase. Th
This is a hardware generator framework that produces synthesizable Verilog for RISC-V designs, serving as a powerful tool for hardware development even though it uses a Scala-based DSL rather than native Verilog for the initial design entry.
ScalaHardware Description FrameworksRISC-V Processor CoresAutomated Hardware Generation - verilator/verilator
verilator/verilator
3,365Auf GitHub ansehenVerilator is a hardware simulation engine and toolchain that translates Verilog and SystemVerilog hardware description languages into optimized C++ or SystemC models. It functions as a compiler and transpiler, converting hardware designs into executable binaries to achieve high-speed simulation and integration into software environments. The project distinguishes itself by focusing on simulation acceleration through the generation of optimized C++ classes and cycle-accurate models. It provides a SystemVerilog linter for static analysis of hardware designs and a hardware coverage analyzer to t
Verilator is a high-performance Verilog and SystemVerilog simulator that provides essential linting and static analysis, though it functions as a compiler-based simulator rather than a full-stack FPGA synthesis suite.
SystemVerilogSimulation AccelerationSource-to-C TranspilersBi-Directional Language Bridging - verilog-to-routing/vtr-verilog-to-routing
verilog-to-routing/vtr-verilog-to-routing
1,241Auf GitHub ansehenThis project is an open-source computer-aided design toolchain designed for the synthesis, placement, and routing of hardware designs onto programmable logic architectures. It serves as a comprehensive framework for research and development, enabling the transformation of hardware description language designs into optimized netlists and physical implementation files. By providing a modular pipeline, the system facilitates the entire flow from initial logic synthesis to the generation of configuration data for programmable hardware devices. The toolchain distinguishes itself through its focus
This is a comprehensive open-source CAD flow for FPGA research that handles the synthesis and implementation of Verilog designs, though it focuses on the backend routing and placement rather than providing a general-purpose Verilog simulator or waveform viewer.
C++HDL Logic SynthesisBitstream GenerationLogic Synthesis Tools
