2 Repos
Awesome GitHub RepositoriesRTL Design
Defining digital logic at the register-transfer level using construction primitives.
Distinct from Quantum Circuit Design: RTL is a specific abstraction level for digital design not covered by the provided candidates.
Explore 2 awesome GitHub repositories matching hardware & iot · RTL Design. Refine with filters or upvote what's useful.
Awesome RTL Design GitHub Repositories
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- chipsalliance/chisel
chipsalliance/chisel
4,691Auf GitHub ansehenChisel is a hardware construction language and description tool used to define digital circuits. It functions as a generator that converts high-level hardware descriptions into synthesizable Verilog code for use in ASIC and FPGA design. The project enables the creation of parameterizable hardware templates and reusable digital components. It leverages functional and object-oriented programming patterns to transform complex circuit representations into finalized hardware descriptions. The toolset covers the register-transfer level design workflow, allowing users to model digital circuits usin
Allows defining digital logic at the register-transfer level using a dedicated set of construction primitives.
Scalachip-generatorchiselchisel3 - yosyshq/picorv32
YosysHQ/picorv32
4,222Auf GitHub ansehenpicorv32 is a size-optimized RISC-V CPU core and synthesizable processor IP designed for integration into FPGA and ASIC hardware designs. It serves as an open-source CPU architecture and embedded system-on-chip component that implements a standard RISC-V instruction set. The design features a modular architecture that allows for the integration of external coprocessors to implement custom non-branching instructions. It includes a parameterized integer unit with configurable multiplication and division cores to balance performance against total logic gate count. The project covers a broad ran
Provides a synthesizable hardware description of the processor core at the register-transfer level.
Verilog
