YosysHQ/yosys
Yosys
Yosys هو أداة تركيب منطق رقمي وتركيب RTL تحول كود لغة وصف الأجهزة إلى تمثيلات على مستوى البوابة محسنة. تعمل كمحسن منطق أجهزة وأداة تحقق رسمية، مما يوفر إطار عمل لتحويل تمثيلات الدوائر العامة إلى خلايا مكتبة تقنية محددة لمنصات الأجهزة المستهدفة.
يخدم المشروع كأداة أتمتة تصميم الأجهزة من خلال بيئة قابلة للبرمجة تُستخدم لتنفيذ تسلسلات من أوامر التركيب. تسمح هذه الأتمتة بإدارة سير عمل الأجهزة الرقمية المعقدة، ودمج تركيب تصميم RTL مع تعيين خلية التكنولوجيا.
تشمل قدرات التحقق والتحليل الخاصة به فحص النموذج الرمزي والتحقق من تكافؤ التصميم. تدعم هذه الأدوات التحقق الرسمي من الأجهزة من خلال فحص خصائص السلامة والحيوية وإنشاء مقاعد اختبار المحاكاة لضمان مطابقة التصميمات لمواصفاتها الأصلية.
Features
- Logic Synthesis Tools - Transforms hardware description language code into optimized gate-level representations for digital circuit design.
- Digital Logic Design Tools - Functions as a comprehensive framework for converting generic circuit representations into specific technology library cells.
- Hardware Design Automation - Automates the sequence of synthesis and verification tasks for digital hardware projects using scripts and APIs.
- Hardware Logic Optimization - Provides optimization passes and dataflow tracking tools to reduce area and increase performance of digital designs.
- Logic Optimizers - Implements dataflow tracking and optimization passes to reduce the area and increase the performance of digital designs.
- RTL Design Tools - Transforms HDL code into optimized gate-level representations through elaboration, flattening, and mapping.
- RTL Elaboration Engines - Provides an elaboration engine that converts high-level hardware description language code into flattened netlists.
- Technology Cell Mapping - Implements a framework for matching generic circuit representations to specific technology library cells for hardware platforms.
- Technology Mapping - Converts generic synthesis results into specific cell libraries to prepare hardware designs for physical implementation.
- Hardware IR Graphs - Uses directed graphs of cells and nets as an intermediate representation for hardware design analysis and transformation.
- Symbolic Model Checking - Verifies hardware design properties by representing states as boolean formulas and solving them using SAT engines.
- Formal Verification Tools - Provides a suite for symbolic model checking and equivalence checking to ensure hardware designs match specifications.
- Hardware Logic Verification - Ensures digital designs match original specifications by checking safety and liveness properties via formal solvers.
- Synthesis Automation Tools - Provides a system for executing sequences of synthesis commands via scripts to automate hardware design processing.
- Pass-Based Optimizations - Employs a modular sequence of optimization passes to iteratively reduce the area and delay of digital circuits.
- Hardware Circuit Equivalence - Uses symbolic model checking to ensure synthesized circuits match their original specifications.
- Synthesis Command Interfaces - Exposes internal synthesis functions as a set of scriptable commands for automating hardware design workflows.
- Liveness Property Verification - Ensures that hardware designs eventually reach desired states or respond to requests within required timeframes.
- Safety - Checks whether hardware assertions hold true over bounded or unbounded time horizons to detect design flaws.
