5 مستودعات
Compilers that automatically transform functional code into parallel execution formats.
Distinct from High-Performance and Parallel Computing: Distinct from general high-performance computing: focuses on the automated transformation of code for parallel hardware.
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Genesis is an embodied AI simulation platform and parallelized robotics simulator designed for training general-purpose robotic agents. It integrates a physics engine for robotics that calculates collisions and movements for rigid bodies, soft tissues, and fluids, alongside a photorealistic 3D rendering engine. The platform features a domain randomization framework to vary environment parameters across parallel simulations, aiding in sim-to-real transfer. It supports the integration of real-world captured light fields and Gaussian splatting to provide photorealistic backgrounds within simulat
Translates high-level functions into optimized parallel kernels for high-performance hardware execution.
Bend is a high-level parallel programming language and compiler designed to execute code across multi-core CPUs and GPUs automatically. By translating functional source code into a graph-based intermediate representation, it enables massive parallel execution without requiring manual management of threads, locks, or atomic operations. The runtime operates as an interaction net engine, where computations are represented as networks of nodes that reduce through local rewriting rules. This model utilizes a work-stealing scheduler to distribute tasks across thousands of hardware threads, ensuring
Translates functional code into a concurrent format to achieve near-ideal speedup on parallel hardware.
Numba هو مترجم فوري (JIT) يترجم دوال Python عالية المستوى إلى كود آلة محسن في وقت التشغيل. من خلال الاستفادة من بنية المترجم LLVM، فإنه يوفر إطار عمل لتسريع معالجة البيانات الرقمية والحسابات الرياضية، مما يتيح مستويات أداء تضاهي اللغات المجمعة استاتيكياً. يتميز المشروع بقدرته على إجراء التخصيص القائم على استنتاج النوع، والذي يولد تعليمات آلة مصممة خصيصاً لأنواع البيانات المستخدمة أثناء التنفيذ. يستخدم خط تجميع كسول يؤجل الترجمة حتى لحظة الاستدعاء، مما يقلل من عبء بدء التشغيل مع الحفاظ على أداء ثابت عبر معماريات المعالجات وأنظمة التشغيل المختلفة. إلى جانب التجميع الأساسي، توفر مجموعة الأدوات دعماً واسعاً لتسريع الأجهزة من خلال توزيع العمليات التكرارية وتعبيرات المصفوفات عبر أنوية CPU متعددة ووحدات معالجة الرسومات. تستخدم استراتيجيات التوجيه (vectorization) والتوازي لزيادة الإنتاجية لمجموعات البيانات الرقمية واسعة النطاق، مما يسمح للمطورين باستهداف الأجهزة المتخصصة مباشرة من الكود القياسي.
Automatically transforms code into parallel execution formats to ensure consistent performance across architectures.
IREE is an MLIR-based compiler toolchain and runtime designed to translate machine learning models from various frameworks into optimized binaries for execution across diverse hardware targets. It provides a unified pipeline to ingest models from PyTorch, TensorFlow, JAX, and ONNX, lowering them into a common intermediate representation for deployment on CPUs, GPUs, and bare-metal embedded systems. The project distinguishes itself through a bytecode virtual machine and a hardware abstraction layer that decouple high-level model logic from specific hardware instruction sets. It supports sophis
Defines structures to represent and optimize parallel execution patterns within a compiled machine learning model.
Tiramisu is a polyhedral C++ compiler framework designed to express and optimize data-parallel algorithms for diverse hardware accelerators. It provides a programming interface that allows developers to define mathematical expressions, manage loop iteration spaces, and organize functions targeting heterogeneous architectures. The system features an advanced compilation infrastructure that abstracts computations into a hardware-agnostic intermediate representation before lowering them into native machine code or hardware configuration bitstreams. It calculates exact data flow dependencies thro
A specialized compiler tool that transforms high-level loop structures and matrix operations to maximize hardware execution efficiency.